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Language

Specify HDL code generation language

Model Configuration Pane: HDL Code Generation

Description

Select the language (VHDL®, Verilog®, or SystemVerilog ) in which code is generated. The selected language is referred to as the target language. When you specify the Language and click the Generate button, HDL Coder™ generates code in that language for the Subsystem that is specified by the Generate HDL for parameter. By default, the HDL code is generated in VHDL language and into the hdlsrc folder.

The generated HDL code complies with these standards:

  • VHDL-1993 (IEEE® 1076-1993)

  • Verilog-2001 (IEEE 1364-2001)

  • SystemVerilog-2005 (IEEE 1800-2005)

Settings

VHDL (default) | Verilog | SystemVerilog

Default: VHDL

VHDL

Generate VHDL code.

Verilog

Generate Verilog code.

SystemVerilog

Generate SystemVerilog code.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate Verilog code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','TargetLanguage','Verilog')
makehdl('sfir_fixed/symmetric_fir')

Programmatic Use

Property: TargetLanguage
Type: character vector
Value: 'VHDL' | 'Verilog' | 'SystemVerilog'
Default: 'VHDL'

Version History

Introduced in R2012a

See Also