Using Altera DSP Builder Advanced Blockset with HDL Coder
This example shows how to use the Altera® DSP Builder Advanced Blockset with HDL Coder™.
Using the Altera® DSP Builder Advanced Blockset Subsystem block, or DSPBA Subsystem block, enables you to model designs using blocks from both Simulink® and Altera®, and to automatically generate integrated HDL code. HDL Coder™ generates HDL code from the Simulink® blocks, and uses Altera® DSP Builder to generate HDL code from the DSPBA Subsystem blocks.
In this example, the design, or code generation subsystem, contains two parts: one with Simulink® native blocks, and one with Altera® DSP Builder Advanced blocks. The Altera® blocks are grouped in a DSPBA Subsystem (hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem). Altera® DSP Builder optimizes these blocks for Altera® FPGAs. In the rest of the design, Simulink® blocks and HDL Coder™ offer many model-based design features, such as distributed pipelining and delay balancing, to perform model-level optimizations.
Setup for Altera® DSP Builder Advanced Blockset
In order to use the Altera® DSP Builder Advanced Blockset Subsystem block, you must have Altera® Quartus II set up with Simulink®. For version compatibility, please refer to the HDL Coder documentation.
Create Altera® DSP Builder Advanced Blockset Subsystem
To create a DSPBA Subsystem:
Put the Altera® blocks in one subsystem and set its architecture to "Module" (the default value).
Place a Device block at the top level of the subsystem. You can have subsystem hierarchy in a DSPBA Subsystem, but there must be a Device block at the top level of the hierarchy.
In this example, a Stateflow chart generates the channel and valid signals to drive the DSPBA subsystem.
Generate HDL Code
You can use either makehdl at the command line or HDL Workflow Advisor to generate HDL code. To use makehdl:
You can also generate a testbench, simulate, and synthesize the design as you would for any other model.
Handle Simulation Mismatch When Valid Signal Not Asserted
The DSPBA Subsystem simulation may not match its generated code's behavior when the valid signal is not asserted under certain circumstances, such as when the folding option in both hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelIn and hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelOut are turned on. The mismatch affects the downstream Simulink design and causes a test bench simulation failure.
To see the mismatch, you can turn the folding setting on the ChannelIn and ChannelOut blocks:
set_param('hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelIn', 'FoldingEnabled', 1); set_param('hdlcoder_sldspba/SLandDSPBA/DSPBA Subsystem/ChannelOut', 'FoldingEnabled', 1);
Then, generate the HDL code and test bench again:
After simulating the generated code and test bench, you can see that the outputs from HDL coder match the reference data only when the valid signal is asserted.
As the message from the test bench indicates, the mismatch is expected.
To avoid this simulation mismatch, insert an enabled subsystem at the DSPBA Subsystem output signals, before they reach the Simulink part of your design or the output ports of the overall design. The following subsystem shows how to connect signals to the enabled subsystem.