setCaptureConditionCombinationOperator

Configure operator that combines individual signal value comparisons into overall capture condition

Since R2024a

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Syntax

setCaptureConditionCombinationOperator(hub,operator)
setCaptureConditionCombinationOperator(hub,operator,DataCaptureName=dataCaptureIPName)

Description

Add-On Required: This feature requires the HDL Verifier Support Package for AMD FPGA and SoC Devices add-on.

setCaptureConditionCombinationOperator(hub,operator) configures the logical operator operator that combines comparisons of individual signals into an overall capture condition for the first data capture IP. DC is a customized data capture hub object.

example

setCaptureConditionCombinationOperator(hub,operator,DataCaptureName=dataCaptureIPName) configures the logical operator operator that combines comparisons of individual signals into an overall capture condition for a data capture IP specified by dataCaptureIPName.

Examples

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This example uses a customized data capture hub object, hub, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2. Each IP defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic for the datacpture1 IP.

setEnableCaptureCtrl(hub,true);

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IPs using the FPGA Data Capture Component Generator tool.

Enable capture condition logic for the datacpture2 IP.

setEnableCaptureCtrl(hub,true,DataCaptureName="datacapture2");

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is equal to 17. Set this condition for the datacapture1 IP.

setCaptureCondition(hub,'A',true,'High');
setCaptureCondition(hub,'B',true,uint8(17));

Combine comparisons of signals A and B into an overall capture condition using an AND operator.

setCaptureConditionCombinationOperator(hub,'AND');

Set up a capture condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is equal to 17. Set this condition for the datacapture2 IP.

setCaptureCondition(hub,'A',true,'High', ...
DataCaptureName="datacapture2");
setCaptureCondition(hub,'B',true,uint8(17), ...
DataCaptureName="datacapture2");

Combine comparisons of signals A and B into an overall capture condition using an AND operator.

setCaptureConditionCombinationOperator(hub,'AND', ...
DataCaptureName="datacapture2");

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Logical operator to combine comparisons of individual signals into a capture condition, specified as 'AND' or 'OR'. The capture condition comprises value comparisons of one or more signals. To combine value comparisons, you can use only one type of logical operator. For example, suppose three signals, A, B, and C, make up the capture condition. The options are:

  • A == 10 AND B == 'Falling edge' AND C == 0
  • A == 10 OR B == 'Falling edge' OR C == 0

You cannot mix and match the combination operators. For details on capture conditions, see Capture Conditions.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a

See Also

Objects

Tools