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Accelerate Communications System Simulation Using FPGA-in-the-Loop

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This example uses FPGA-in-the-loop (FIL) simulation to accelerate part of a communications system. The application uses the Viterbi algorithm to decode a convolutional encoded random stream that is BPSK modulated, sent through an AWGN channel, and then demodulated. Using a sample-by-sample approach leads to a modest speedup over normal Simulink® simulation, while using the "Process as Frames" option leads to further speedup.

Requirements and Prerequisites

Tools required to run this example:

  • FPGA design software (AMD® ISE® design suite, AMD Vivado® design suite, Intel® Quartus® II design software, or Microchip Libero® SoC design software), with a supported version listed in FPGA Verification Requirements.

  • One of the supported FPGA development boards. For supported hardware, see Supported FPGA Devices for FPGA Verification.

  • For connection using Ethernet: Gigabit Ethernet Adapter installed on host computer, Gigabit Ethernet crossover cable

  • For connection using JTAG: USB Blaster I or II cable and driver for Intel FPGA boards. Digilent® JTAG cable and driver for AMD FPGA boards.

  • For connection using PCI Express®: FPGA board installed into PCI Express slot of host computer.

  • For connection using USB Ethernet: USB 3.0 or 2.0 cable compatible with the target board.

After the installer completes the support package installation, it guides you through the process of establishing communication with the hardware board. Complete the setup process for the selected hardware board and connection type. For more information about the setup steps, see Guided Hardware Setup.

1. Open and Execute the Simulink Model

Open the model. Due to the large quantity of data to process, the simulation takes approximately 9 seconds without FIL. This example improves the simulation speed in the following steps by using the FIL.

2. Generate HDL Code

This step requires HDL Coder™. If you do not have HDL Coder, you can use pre-generated HDL files in the current directory.

If you use these copied files, go directly to step 3.

Generate HDL code for the Viterbi block subsystem by performing these steps:

a. Right click on the existing FIL block labeled viterbi_block1. Click on Comment Out to remove this block for code generation.

b. In the Modeling tab, click Model Settings.

d. Click on the HDL Code Generation pane and make sure the hdlcoderviterbi_for_fil/viterbi_block is selected.

e. Click Generate.

Alternatively, you can generate HDL code by entering the following command at the MATLAB® prompt:

makehdl('hdlcoderviterbi_for_fil/viterbi_block')

3. Set FPGA Design Software Environment

Before using FIL, make sure your system environment is set up properly for accessing FPGA design software. You can use the function hdlsetuptoolpath to add FPGA design software to the system path for the current MATLAB session. Below are example command lines for each tool. Substitute with your actual executable if it is different.

For AMD FPGA boards using ISE design software, run:

hdlsetuptoolpath('ToolName','Xilinx ISE','ToolPath','C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\ise.exe');

For AMD FPGA boards using Vivado design software, run:

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2023.1\bin\vivado.bat');

For Intel boards, run:

hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\22.1.1\quartus\bin\quartus.exe');

For Microchip boards, run:

hdlsetuptoolpath('ToolName','Microchip Libero SoC','ToolPath','C:\Microsemi\Libero_SoC_v23.2\Designer\bin\libero.exe');

4. Run FIL Wizard

To launch the FIL Wizard, enter the following command at the MATLAB prompt:

filWizard;

4.1 Specify Hardware Options in FIL Wizard

Set the FIL options for the FPGA development board.

1. Specify whether the wizard generates a FIL Simulink block or a FIL Simulation MATLAB System object™. For this example, in the FIL simulation with section, select Simulink.

2. For Board Name, select the FPGA development board connected to your host computer. If your board is not on the list, select one of the following options:

  • Get more boards... to download the FPGA board support package(s) (this option starts the Support Package Installer).

  • Create custom board... to create the FPGA board definition file for your FPGA board (this option starts the New FPGA Board Wizard).

3. Select the connection for simulation. The available connection methods are JTAG, Ethernet, PCIe, and USB Ethernet. Not all boards support all connection methods. For the full list of supported boards and connection methods, see Supported FPGA Devices for FPGA Verification.

4.USB Ethernet connection only: The USB controller on the Zynq® board can function as a host or device. The DTB used for the FIL workflow configures it as a USB Ethernet device. When the board is connected to the host computer using the USB port, it enumerates as a network adapter named Mathworks USB Ethernet/RNDIS Gadget.The configuration of this network adapter on the host is automated using the DHCP service that runs on the Zynq board.

5. Click Next to continue.

4.2 Source Files

a. Add all the previously generated HDL source files for the Viterbi Block subsystem.

b. Select the file viterbi_block.vhd as the top-level file. You may need to make the FIL Wizard window wider in order to see these options.

c. Notice that the viterbi_block has been entered for you as the default top-level module name. Click Next to continue.

d. Click Next to continue.

4.3 DUT I/O Ports

Review the port listing. If the parser assigned an incorrect port type for any given port, you can manually change the signal. Click Next to continue.

4.4 Build Options

a. Select an output folder.

b. Click Build to build the FIL block and programming file.

During the build process, the following actions occur:

  • A FIL block named viterbi_block is generated in a new model.

  • After new model generation, the FIL Wizard opens a command window where the FPGA design software performs synthesis, mapping, place-and-route, timing analysis, and FPGA programming file generation. For this block, these steps take about 20 minutes.

When the FPGA design software process is finished, a message in the command window notifies you that you can close the window.

5. Open and Complete Simulink Model for FIL

a. Open the hdlcoderviterbi_for_fil.slx.

b. Copy the previously generated FIL block into this model. Replace viterbi_block1 with the new FIL block. Note that the original block has the inputs on the right. To make the FIL block have its inputs on the right, right-click the block, and then select Format > Flip Block.

6. Configure FIL Block

a. Double-click the FIL block in the model to open the block mask.

b. Click Load.

To program the FPGA boards, use a JTAG cable. To program the Zynq boards, use a JTAG cable for the JTAG connection, an Ethernet cable for the Ethernet connection, and a USB cable for the USB Ethernet connection. If the board is set up correctly, a message window indicates that the FPGA programming file has been loaded successfully. Click OK to dismiss this dialog box.

c. Click OK to close the block mask.

7. Run FIL Simulation

a. Uncomment hdlcoderviterbi_for_fil/viterbi_block to run the simulation with only the FIL block. To perform this action, right-click the block and then select Comment Out.

b. Run the simulation for 20480 seconds and observe the performance.

FrameSize = 1;
tic;
sim('hdlcoderviterbi_for_fil');
fs1 = toc

You can try setting the frame size to a larger number. For this example, the frame size is set to 1024 bytes.

FrameSize = 1024;
tic;
sim('hdlcoderviterbi_for_fil');
fs2 = toc

In our tests on Windows, for USB Ethernet on AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, the time to simulate was around 232 seconds when FrameSize = 1.However, the simulation time was decreased to around 4.5 seconds when the frame size was increased to 1024, which is almost half the time as simulating in Simulink without FIL. When FrameSize = 1024, this particular board and system gives a speedup of around 50 times. Note that other boards and communications system may be even faster.

speedup = fs1 / fs2

By adding more blocks to the FIL part of the design and minimizing the use of Simulink scopes and displays, you can achieve even greater speedups.

This concludes the Accelerating Communications System Simulation Using FPGA-In-the-Loop example.