UVM Generation
R2026bGenerate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.
Generate a UVM top model with a testbench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.
Generate UVM test components, and integrate them into your existing UVM environment.
To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.
Not all UVM generation functionalities are available in MATLAB Online™.
Functions
Blocks
 | Sequence Feedback | Connect between scoreboard and sequence in UVM testbench model (Since R2023a) |
Objects
uvmconfig | UVM configuration object |
svdpiConfiguration | Configure workflows for UVM and SystemVerilog component generation from MATLAB (Since R2023a) |
DPICustomTemplateConfiguration | Configure custom template for Simulink DPI component generation (Since R2026b) |
uvmfTestBenchConfiguration | Configure YAML generation from DPI component generation and its integration with UVMF (Since R2024a) |
Model Settings
Topics
UVM Generation from Simulink
- UVM Component Generation Overview
Generate a Universal Verification Methodology (UVM) environment from a Simulink model. - Customize Generated UVM Code
Customize file banners and HDL simulation timescale when generating a UVM testbench. - Generate SystemVerilog Assertions and Functional Coverage
Generate SystemVerilog immediate assertions fromverifystatements and model verification blocks, and collect functional coverage information (requires Simulink Test™ license). - Use Tunable Parameters to Generalize UVM Simulation
Generate UVM parameters from Simulink tunable parameters. - Tunable Parameters in Sequence Subsystem
Generate random constraint parameters in UVM sequence from Simulink tunable parameters. - Tunable Parameters in Scoreboard Subsystem
Generate random constraint parameters in UVM scoreboard from Simulink tunable parameters. - Generate Individual UVM Component from Simulink
Generate a Universal Verification Methodology (UVM) component from a Simulink model. - Use Custom Template to Generate DPI Component
This example shows how to create a custom target language compiler (TLC) template for a Simulink® model and generate a SystemVerilog DPI component from it.
UVM Generation from MATLAB
- SystemVerilog and UVM Templates
Generate customizable SystemVerilog modules and UVM components from MATLAB using templates. - Custom Template Language Syntax
Template variable definition and usage. - Generate Cross-Platform UVM Components
Generate the UVM components for a Linux® operating system from your Windows® host machine.
UVM Framework
- Prepare DUT for UVM Framework Generation
DUT requirements for UVMF generation.
Featured Examples
Use Templates to Create SystemVerilog DPI and UVM Components
Generate SystemVerilog direct programming interface (DPI) and universal verification methodology (UVM) components from MATLAB® functions using built-in templates. This example also reviews the generated SystemVerilog and how it relates to the template. This example teaches you basic template capabilities, that you can use to create a custom template.
Generate Parameterized UVM Testbench from Simulink
Develop a design and testbench in Simulink® and generate an equivalent simulation for a universal verification methodology (UVM) environment using uvmbuild. You can then extend this testbench to refine your verification using protocol-specific drivers, constrained random sequences, and parameterized scoreboards.
Replace Behavioral DUT with RTL DUT in UVM Testbench
Move from a stand-in C-based design DUT to a simple behavioral RTL DUT interface to a full protocol-based RTL DUT interface that uses AXI4-Lite and AXI4-Stream bus protocols. Several of the UVM components must change, such as the driver and monitor, but you can use reuse the original testbench structure and the sequence and scoreboard components without modification.
Add Random Constraints to Sequences in UVM Testbench
Add constrained random verification to a universal verification methodology (UVM) testbench generated from Simulink®. Both Simulink parameters and input ports to the stimulus generation results in randomizable sequence class data members in the UVM testbench. Through standard UVM class inheritance and factory overrides, the design verification engineer can add new and valuable constrained random test cases to their UVM test suite.
Change Parameters and Coverage Goals of Scoreboard in UVM Testbench
Control the parameters of the response checker in a UVM testbench generated from Simulink®. Such parameterization helps the design verification engineer reuse the scoreboard under different testing scenarios. Simulink parameters to the checker will result in a configuration object whose values can be set in a derived test class (randomized or not) or directly via a command line plusarg.
Include Driver and Monitor in UVM Test Bench
Uses the uvmbuild function to generate a Universal Verification Methodology (UVM) test bench, which includes a UVM driver and monitor from a Simulink® design and test bench.
Integrate SystemVerilog DPI into UVM Framework Workflow
Generate reusable verification components from a Simulink® model as SystemVerilog DPI components using HDL Verifier™ software. You use the MATLAB-to-UVMF (mtlb2uvmf) workflow to create Universal Verification Methodology (UVM) testbenches quickly. For more information on mtlb2uvmf workflow, see MathWorks Integration from Siemens Verification Academy.
Generate UVM Framework Testbench for Block-Level Verification
Generate DPI components for a UVM sequence and predictor, and integrate them into a UVM framework (UVMF) testbench for block-level verification. The workflow follows these steps:
Integrate DPI Components with Custom Predictors for UVM Framework
Integrate DPI sequence component with custom predictor component and generate fully functional UVM framework (UVMF) testbench.
