slvnvlogsignals

Log test data for component or model during simulation

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Syntax

data = slvnvlogsignals(model_block)
data = slvnvlogsignals(harness_model)
data = slvnvlogsignals(harness_model,test_case_index)

Description

data = slvnvlogsignals(model_block) simulates the model that contains model_block and logs the input signals to the model_block block. model_block must be a Simulink® Model block.

data = slvnvlogsignals(harness_model) simulates every test case in harness_model and logs the input signals to the Test Unit block in the harness model. Generate harness_model by using the Simulink Design Verifier™ analysis, sldvmakeharness (Simulink Design Verifier), or slvnvmakeharness.

data = slvnvlogsignals(harness_model,test_case_index) simulates every test case in the Signal Editor block of the harness_model specified by test_case_index. slvnvlogsignals logs the input signals to the Test Unit block in the harness model. If you omit test_case_index, slvnvlogsignals simulates every test case in the Signal Editor.

example

Examples

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This example shows how to log simulation data for a Model block and use the logged data to create a harness model and visualize the data in the referenced model.

Open the project that contains the example files and the model named sldemo_mdlref_basic.

openExample('simulink_features/ComponentBasedModelingUsingModelReferenceExample')
openProject('ModelReference');

Log the signals for the block named CounterB.

data = slvnvlogsignals('sldemo_mdlref_basic/CounterB');

Create a harness model for sldemo_mdlref_counter using the logged data and the default harness options.

load_system('sldemo_mdlref_counter');
harnessOpts = slvnvharnessopts
[harnessFilePath]  = ...
    slvnvmakeharness('sldemo_mdlref_counter', data, ...
    harnessOpts);

Input Arguments

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The full block path name or handle to a Simulink Model block, specified as a character vector or string.

Name or handle to a harness model that the Simulink Design Verifier software, sldvmakeharness (Simulink Design Verifier), or slvnvmakeharness creates, specified as a character vector or string.

Array of integers that specifies which test cases in the Signal Editor block of the harness model to simulate.

Output Arguments

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Structure that contains the logged data.

Version History

Introduced in R2010b

See Also

(Simulink Design Verifier) | | |