Prácticas recomendadas para análisis de Simulink Design Verifier
Prácticas recomendadas, consideraciones y limitaciones de soporte para análisis de Simulink® Design Verifier™
Simulink Design Verifier proporciona distintos niveles de compatibilidad para las funcionalidades de Simulink. Si el modelo contiene bloques parcialmente admitidos, puede habilitar el procesamiento automático con stubs o evitar utilizar funcionalidades no admitidas en los modelos que analice.
Temas
Prácticas recomendadas y consideraciones
- Simulink Design Verifier Block Library
Accessing the Simulink Design Verifier block library. - Handle Incompatibilities with Automatic Stubbing
How to use automatic stubbing. - Modified Condition and Decision Coverage in Simulink Design Verifier
Describes the difference between MCDC coverage in Simulink Design Verifier and in Simulink Coverage™. - Enhanced MCDC Coverage in Simulink Design Verifier
Describes the Enhanced MCDC coverage concept and workflows. - Analyze Model for Enhanced MCDC Analysis
Analyze a model for enhanced MCDC objectives. - Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks. - How Simulink Design Verifier Reports Approximations Through Validation Results
Describes how Simulink Design Verifier reports approximations through validation results.
Detalles sobre las limitaciones de soporte
- Support Limitations of Simulink Design Verifier for Simulink Software Features
Lists Simulink software features that Simulink Design Verifier does not support. - Supported and Unsupported Simulink Blocks in Simulink Design Verifier
Lists Simulink blocks that Simulink Design Verifier does and does not support. - Support Limitations for Model Blocks
Simulink Design Verifier supports the Model block with some limitations. - Support Limitations for Stateflow Software Features
Lists the Stateflow® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support. - Support Limitations for MATLAB for Code Generation
Lists limitations associated with Simulink Design Verifier software support for MATLAB® for code generation. - Support Limitations and Considerations for S-Functions and C/C++ Code
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier. - Analyze Models with Counters and Timers
Best practices for handling counters and timers in your model to avoid over complicating Simulink Design Verifier analysis. - Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.
