Memory
R2026bSoC Blockset™ for AMD enables simulation and evaluation of shared memory transactions in Simulink®. Visualize post-simulation performance and bandwidth metrics before deploying to SoC device by using the Logic Analyzer app.
Blocks
 | AXI4 Random Access Memory | Model random access through external memory (Since R2022b) |
 | AXI4-Stream to Software | Stream AXI4 data from FPGA to software (Since R2022b) |
 | Software to AXI4-Stream | Stream AXI4 data from software to FPGA (Since R2022b) |
 | AXI4 Video Frame Buffer | Model connection between two hardware algorithms through external memory (Since R2022b) |
 | Memory Traffic Generator | Generate traffic towards memory controller |
 | Register Channel | Timing model for transfer of register values |
 | Interrupt Channel | Send interrupt to processor from hardware |
 | AXI4 Master Sink | Receive random access memory data |
 | AXI4 Master Source | Generate random access memory data |
 | Stream Data Sink | Receive continuous stream data |
 | Stream Data Source | Generate continuous stream data |
 | IP Core Register Read | Model register writes from software to hardware |
 | SoC Bus Selector | Convert bus to control signals |
 | SoC Bus Creator | Convert control signals to bus |
 | Stream FIFO | Control backpressure between hardware logic and upstream data interface |
 | Stream Connector | Connect two IPs with data streaming interfaces |
 | Register Read | Read data from a register region on the specified IP core |
 | Register Write | Write data to a register region on the specified IP core |
 | Stream Read | Stream data from shared memory to processor algorithms |
 | Stream Write | Stream data from processor algorithms to shared memory |
 | Video Stream FIFO | Control backpressure between hardware logic and upstream video interface |
 | Video Stream Connector | Connect two IPs with video streaming interfaces |
Apps
| Logic Analyzer | Visualize, measure, and analyze transitions and states over time |
Tools
| Performance Report | Display performance and core usage metrics after model simulation or execution on SoC device |
Model Settings
Topics
Design
- Memory and Register Data Transfers
Introduction to memory and register transfers. - External Memory Channel Protocols
Supported memory channel protocols and control signals. - AXI4-Stream Interface
How to design your model for AXI4-Stream vector or scalar interface generation. - Simplified AXI4 Master Interface
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces. - AXI4-Stream Video Interface
How to design your model for IP core generation with AXI4-stream video interfaces.
Simulation
- Simulation Diagnostics
SoC Blockset for AMD enables simulation and evaluation of memory transactions in Simulink without the need to deploy a model to an SoC device. - Simulation Performance Tips
Suggestions for enhancing simulation performance of SoC models. - Simulation Performance Plots
SoC Blockset for AMD enables post-simulation analysis of memory diagnostic data.
Measurement
- Memory Performance Information from FPGA Execution
Obtain memory interconnect traffic information from a design running on FPGA.
Featured Examples
Random Access of External Memory Using AMD Devices
Model external memory accesses from FPGA for rotating an ASCII art image. Many applications require FPGA to access memory in random fashion as per the requirements of algorithm. You will learn how to design memory address generation along with other AXI4 master signals to read and write specific regions of memory using SoC Blockset™ for AMD. You will simulate, implement and verify your design on hardware.
Histogram Equalization Using Video Frame Buffer
Perform histogram equalization with HDMI input and output and using external memory for video frame buffering.
Accelerate SoC Simulation by Varying Abstraction Levels
Different levels of abstraction available for SoC architecture and how to accelerate the simulation speed of SoC models by choosing the right abstraction level.
Analyze Memory Bandwidth Using Traffic Generators
Demonstrates how to analyze memory bandwidth for an SoC application. In memory-intensive hardware designs, you may have multiple initiators accessing a common DDR memory. In such cases, it is important to analyze the dynamic requirement of all memory initiators to guide algorithm design and hardware board requirement for deployment. You can simulate the memory traffic using Memory traffic generators, analyze the bandwidth usage and verify it on the hardware.
Receive Signal Waveform Using DDR4 on Xilinx RFSoC Device
Design, simulate, and deploy a system to write and read the captured RF samples from external double data rate 4 (DDR4) memory in Simulink® with an SoC Blockset for AMD implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit. In this example, you can write the captured samples of an analog-to-digital converter (ADC) into external programmable logic (PL) DDR4 memory, read the samples from the PL DDR4 memory, and send them to the processor to display. A tone signal is generated in FPGA using a numerically controlled oscillator (NCO) to verify the receive path.
