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DVB-S2 LDPC Decoder

Decode LDPC code according to DVB-S2 standard

  • Library:
  • Wireless HDL Toolbox / Error Detection and Correction

  • DVB-S2 LDPC Decoder block

Description

The DVB-S2 LPDC Decoder block implements a low-density parity-check (LDPC) decoder using layered belief propagation with min-sum approximation and normalized min-sum approximation algorithms for decoding LDPC codes according to the Digital Video Broadcast Satellite Second Generation (DVB-S2) standard. The block accepts log-likelihood ratio (LLR) values, a stream of control signals, a frame type, and a code rate as inputs and outputs decoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.

The DVB-S2 LPDC Decoder block supports early termination to help improve decoding performance and convergence speeds at high signal-to-noise-ratio (SNR) conditions. The block supports scalar values through the input/output (I/O) interface. It also supports forward error correction (FEC) frames of type normal and short with all the code rates supported by the DVB-S2 standard. For more information about the DVB-S2 standard, see [1].

The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in DVB-S2 modem development.

Ports

Input

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LLR values, specified as a scalar.

For HDL code generation, specify this value in signed fixed-point format. The input word length must be in the range from 4 to 16.

Data Types: int8 | int16 | signed fixed point

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the input frame

  • end — Indicates the end of the input frame

  • valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Type of FEC frame, specified as a Boolean scalar.

  • 0 — Indicates a normal frame

  • 1 — Indicates a short frame

Dependencies

To enable this port, set the FEC frame source parameter to Input port.

Data Types: Boolean

Code rate index, specified as an integer. Code rate index values range from 0 to 10. Each code rate index value represents a specific code rate, as shown in this table.

codeRateIdx ValueCode Rate
0 1/4
11/3
22/5
31/2
4 3/5
52/3
63/4
74/5
85/6
98/9
109/10 (not supported for short frame)

You must specify this value in the fixdt(0,4,0) format.

Dependencies

To enable this port, do one of the following:

  • Set the FEC frame source parameter to Input port.

  • Set the FEC frame source parameter to Property and the Code rate source parameter to Input port.

Data Types: fixdt(0,4,0)

Number of iterations, specified as an unsigned integer in the range from 1 to 63.

If you specify an iter value greater than 63 or less than 1, the block overrides your specification and sets the iter value to 8 before decoding.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Max or Early and the Source for number of iterations parameter to Input port.

Data Types: uint8

Output

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Decoded bits, returned as a Boolean scalar.

Data Types: Boolean

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

  • start — Indicates the start of the output frame

  • end — Indicates the end of the output frame

  • valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.

  • 0 — Indicates that the parity check failed

  • 1 — Indicates that the parity check passed

Dependencies

To enable this port, select the Enable parity check output port parameter.

Data Types: Boolean

Actual number of iterations the block takes to decode the output, returned as a scalar.

Dependencies

To enable this port, set the Decoding termination criteria parameter to Early.

Data Types: uint8

Parameters

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Select the FEC frame source as Input port or Property.

  • Property — Select this option to enable the FEC frame type parameter.

  • Input port — Select this option to enable the frameType port.

Select the FEC frame type as Normal or Short.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Select the code rate source as Property or Input port.

  • Property — Select this option to enable the Code rate parameter.

  • Input port — Select this option to enable the codeRateIdx port.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property.

Select the code rate.

Note

Code rate of 9/10 is not supported for short frame.

Dependencies

To enable this parameter, set the FEC frame source parameter to Property and set the Code rate source parameter to Property.

Select the type of LDPC decoding algorithm. For more information, see Algorithm.

  • Min-sum — Use this option to select the layered belief propagation algorithm with a min-sum approximation. For more information, see Min-Sum Approximation.

  • Normalized min-sum — Use this option to select the layered belief propagation algorithm with a normalized min-sum approximation. For more information, see Normalized Min-Sum Approximation.

Specify the scaling factor as a scalar in the range 0.5 to 1, incremented by 0.0625.

Dependencies

To enable this parameter, set the Algorithm parameter to Normalized min-sum.

Select the decoding termination criteria.

  • Max — Terminate decoding when the block reaches the number of iterations specified in the block mask or through the iter input port.

  • Early — Terminate decoding when the block meets all of the parity checks or when the block reaches the maximum number of iterations provided in the block mask.

Select the source for specifying the number of iterations.

You can set the number of iterations by using either an input port or a parameter.

  • Property — Select this option to enable the Number of iterations parameter.

  • Input port — Select this option to enable the iter port.

Specify the number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Max and the Source for number of iterations parameter to Property.

Specify the maximum number of decoding iterations.

Dependencies

To enable this parameter, set the Decoding termination criteria parameter to Early and set the Source for number of iterations parameter to Property.

Select this parameter to enable the parityCheck output port to view the status of the parity check.

Algorithms

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This figure shows the architecture block diagram of the DVB-S2 LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and the Check node RAM block stores the check node (CN) messages. The Functional Unit block calculates the VN messages and CN messages based on layered belief propagation and either the normalized min-sum approximation algorithm or the min-sum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration. For more information about decoding algorithms, see the following sections.

DVB-S2 LDPC decoder block architecture

References

[1] ETSI Standard EN 302 307 V1.4.1: Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), European Telecommunications Standards Institute, Valbonne, France, 2005-03.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.

[3] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop On Signal Processing Systems, 2004. SIPS 2004, 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.

[4] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved Min-Sum Decoding Algorithms for Irregular LPDC Codes." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. https://doi: 10.1109/ISIT.2005.1523374.

Extended Capabilities

Version History

Introduced in R2022a

See Also

Blocks