vhdl/verilog simulink

Is there any way that i import a vhdl/verilog code to a simulink block and use that block as a subsytem?

Answer 1

[Kaustubha Govind]

Provided that you already have HDL simulator software like ModelSim or Incisive installed, you can use EDA Simulator Link to achieve the interface. The product library comes with a HDL Cosimulation block that you can run as part of a Simulink model.

Answer 2

[Tim McBrayer]

If you don't have the need to cosimulate with an HDL simulator but wish to incorporate hand-written HDL code with code generated by HDL Coder, you can choose the 'Black Box' architecture for a subsystem, and use your hand-written code as the HDL implementation for that subsystem.

[Sam]

Is any documents to show integrating hand-written HDL code with "Black Box"? I cannot find any tutorials or examples.

[Kaustubha Govind]

See http://www.mathworks.com/help/toolbox/slhdlcoder/bso3rab-1.html

Answer 3

[Edward]

I've walked through the simple inverter.vhd tutorial using the EDA Link to cosimulate with modelsim:

http://www.mathworks.com/help/releases/R2010a/toolbox/edalink/ug/bsctzv_-63.html#bsctzv_-66

I have MATALB R2010a

I am very frustrated because none of the vsim or vsimulink commands work. They just give errors even though I am following the simulation step by step.

I seem to have difficulty getting Modelsim to commiunicate information to MATLAB through the socket interface.

[Kaustubha Govind]

Edward - please create a new question for this issue. Also, it would be useful to paste the exact error messages that you receive.

Answer 4

[VN]

I think Xilinx System Generator can be used for same.

Read the following article, which gives

Step-by-Step Description for MATLAB+ISE Co-Simulation using System Generator for Spartan/Virtex FPGAs with SCREENSHOTS

Find the article at http://wp.me/p1iZg8-3B

I hope this will help,

Share your views -- Vihang Naik, M.Tech II Instrumentation & Control, Embedded Design Center, College of Engineering Pune. naikvihang.wordpress.com