SoC Builder Error: The specified key is not present in this container.

Hi All,

This is something only occurs to me after the big 2023b update. Everytime I try to rebuild my SoC Design, SoC Builder does not allow me to rebuild with the attached error. It happens only after I succesfully built the project, I tried other build options as well but did not help.

Other things I have already tried were to delete all the cache files (like *.slxc...) and folders (like slprj...).

The only solution I have right now is to copy the original project everytime i want to have a new build, which is unproductive.

At the moment, I suspect this might be because my project was upgraded from .2023a to .2023b and there might have been a clash. I will try to build a new project from scratch with .2023b. However, it would also be nice if you could tell me more about this error. Do not think I can share the project here because of size limit. Please reach out by email if you could and i will send you over email.

Regards,

Vu.

[Jacob Mazur]

Hi Vu,

Sorry to hear you're experiencing this issue. Please reach out to our technical support team and we'd be happy to assist: https://www.mathworks.com/support/contact_us.html

If possible, please provide the following in your email:

1. The output of executing "ver -support" in the MATLAB Command Window.
2. Any model and code files you are able to share. If your project is larger than the attachment size limit, we can create a dropbox for you to upload the files to separately.

Thanks, Jacob

[Vu Hoang Thang Chau]

Hi Jacob,

I think I fixed this problem.

The problem can be elaborated as this, and hope it is useful for others.

SoC Build treats Subsystems inside the FPGA model at the top level as IP Cores when generated by SoC Builder. However, you cannot directly create Subsystems (IP Cores) as Enabled Subsystems, because this will cause the shown error. In order to solve this problem I have used a sub-subsystem in the IP Cores subsystems.

Hope this helps.

Regards,

Vu.

[Sergei]

Hello, @Vu Hoang Thang Chau!

I am having the same problem now, and I am also using an enabled subsystem in my FPGA model. Thank you a lot for your answer, creating a subsystem (IP core) wrapper for my enabled subsystem helped and now the model builds)

Best regards