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Kiran Kintali


Last seen: Today

MathWorks

312 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Contributions in
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Answered
Getting Started with Targeting Xilinx Zynq Platform
(follow up from my team) Hi Kiran, I think I might know the issue. In one of the images, I can see the Tool Version text box...

11 días ago | 0

Answered
Slow simulation time ins simulink.
“How do I model the clock signal?” – is a question frequently asked by hardware engineers who are new to using Simulink and HDL ...

13 días ago | 0

| accepted

Answered
Field oriented control speed controller hdl conversion
Field-Oriented Control of a Permanent Magnet Synchronous Machine In this example you will review a Field-Oriented Control (FOC)...

13 días ago | 0

| accepted

Answered
Getting Started with Targeting Xilinx Zynq Platform
The error essage seems to indicate this is an issue with Xilinx Vivado installation? Task "Vivado IP Packager" unsuccessful. ...

13 días ago | 0

Answered
HDL Workflow Advisor Error from inf SampleTime
This issue is actively resolved. Please reach out to support@mathworks.com for additional support on this issue. Thanks

13 días ago | 0

Answered
HDL coder and Embedded coder interaction
If your target hardware requires you to generate C and HDL code it is better to split your design into two subsystems or two mod...

13 días ago | 0

| accepted

Answered
Sampling rate conversion issues in HDL coder
See attached QPSK Tx, Rx example that works with HDL Coder. You can read through instructions in QPSKTxRxHDLExample.m on how to...

26 días ago | 0

Answered
instrumented MEX function...and HDL code...
The original question is related to floating point to fixed point conversion in MALTAB and is now resolved. The followups respon...

27 días ago | 0

Answered
Simulink HDL coder Results compare
If you continue to face the issue please search for Gain block related HDL Coder bug fix by your release here. https://www.math...

27 días ago | 0

Answered
HDL Coder black box inclusion of module with parameterised packed input
>> I considered just using the Bit Concat block and then using the Extract Bits block within the model of the black box, but tha...

27 días ago | 0

Answered
About HDL simulink coder for StateFlow
Attached model describes how to model either edge in Stateflow suitable for HDL code generation. HDL Verision Result C...

27 días ago | 0

Answered
Fixed point to float point conversion of 16 point ifft
See attached example for additional modeling guidelines for MATLAB to HDL.

27 días ago | 0

Answered
Error creading HDL from subsystem
This is a model compilation issue and not HDL Code generation issue. Press ctrl-d or compile the model and make sure there are n...

27 días ago | 0

Answered
HDL Coder: Fails to generate high-level timing support
You have encountered a bug in critical path estimation. However there are no active records with the signature currently active ...

27 días ago | 0

Answered
Create matrix 64x64 that supported by HDL coder
Performing Large Matrix Operation on FPGA web(fullfile(docroot, 'hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-e...

27 días ago | 0

Answered
Define global constant for HDL Coder
Globals are not currently supported in HDL Coder. Use persistent variables instead. Also see this example on how to >> mlhdlc...

27 días ago | 0

Answered
RAM-based shift register in HDL coder
UseRAM parameter: The UseRAM implementation parameter in Simulink HDL block option enables using RAM-based mapping for an intege...

27 días ago | 0

Answered
Implement Reset in Simulink
These page describes how to generate code with synchronous or asynchronous reset. web(fullfile(docroot, 'hdlcoder/ug/reset-and-...

27 días ago | 0

Answered
I want to convert the following code to verilog using hdl coder, please help
The above MATLAB example is poorly written to be taken to HDL code generation. First divide your code into design (DUT) and tes...

27 días ago | 0

Answered
I can't find QPSK timing recovery model example built with Simulink® and Xilinx System Generator for DSP™
This is a Xilinx System Generator support question. Please contact xilinx. https://www.xilinx.com/products/design-tools/vivado/...

27 días ago | 0

Answered
SoC Blockset Support Package for Xilinx Devices Installation Error
If you cotinue to have this issue, please reach out to install support team support@mathworks.com

27 días ago | 0

| accepted

Answered
simulink_hdl_coder says unable to check out license, even though the tool has that license checked-out
We are not aware of such license checkout issue. Please reach out to support@mathworks.com if you continue to face issues and ...

27 días ago | 0

Answered
hdl coder ram usage and source optimizaion
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide Refer to Block RAM mapping guid...

27 días ago | 0

Answered
DE-10 Nano development kit
Board and Reference Design Registration System System for defining and registering boards and reference designs. Register a Cu...

alrededor de 1 mes ago | 0

Answered
Error when I click on build model in SIMULINK
This seems to be Xilinx ISE synthesis tool installation issue; please check your installation and contact Xilinx customer suppor...

alrededor de 1 mes ago | 0

Answered
Error in simulnk: Action types are not supported
This question has two parts: Does HDL Coder currently support "Fuzzy Logic Controller"? Does HDL Coder support "If" Action su...

alrededor de 1 mes ago | 0

Answered
How to do speed optimizations with/in feedback Loops? -Simulink HDL Coder
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features. https://www.mat...

alrededor de 1 mes ago | 0

Answered
timing loops found by synthesis tool when using sqrt function block in hdl coder
This is now fully resolved in R2020b release. Sqrt operation is fully pipelined and several custom latency options for a range o...

alrededor de 1 mes ago | 1

Answered
HDLコード変換した演算ブロックの動作について
(Translation) When HDL code is generated for a Simulink model in HDL Coder (native floating point mode) It seems that the code ...

alrededor de 1 mes ago | 0

Answered
Is there something like code replacement when using HDL Coder?
The simplest approach for incorporating external IP into your HDL Coder Design is to create a black box interface for a subs...

alrededor de 1 mes ago | 0

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