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Kiran Kintali

Last seen: Today Active since 2011

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Answered
Which versions of Xilinx Vivado are supported with which release of HDL Workflow Advisor?
https://www.mathworks.com/help/hdlcoder/supported-hardware.html The supported official versions of Simulation and Synthesis too...

alrededor de 14 horas ago | 0

Answered
Bitstream generation problem in HDL coder
Is it possible to attach a sample model? Feel free to reach out to MathWorks technical support on this question.

alrededor de 14 horas ago | 0

Answered
up sample Simulink doesn't implement rate convertion on hdl coder
Please share your model. I do not see any such errors with a basic model with your sample settings.

7 días ago | 0

Answered
Can HDL coder produce code for unit delay with initial condition input
This feature is not currently supported and is on the future HDL Coder roadmap. For the block 'model/DUTSubsystem/Delay' ...

7 días ago | 0

Answered
PMSM is programed in FPGA using HDL coder.
In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and th...

15 días ago | 0

Answered
PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

20 días ago | 0

Answered
Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

26 días ago | 0

Answered
The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

26 días ago | 0

Answered
makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

alrededor de 1 mes ago | 0

Answered
What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

alrededor de 1 mes ago | 0

Answered
How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

alrededor de 1 mes ago | 1

| accepted

Answered
Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

alrededor de 2 meses ago | 0

Answered
how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

alrededor de 2 meses ago | 0

Answered
How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...

alrededor de 2 meses ago | 0

Answered
Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

3 meses ago | 1

Answered
HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

3 meses ago | 0

Answered
Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

3 meses ago | 0

Answered
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

3 meses ago | 0

Answered
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

3 meses ago | 0

Answered
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 0

Answered
Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

3 meses ago | 1

Answered
How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...

3 meses ago | 0

| accepted

Answered
HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...

3 meses ago | 0

Answered
HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

4 meses ago | 1

| accepted

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