Respondida
Simulink HDL Coder D-FF With Trigger that isn't clock
Can you share a sample model?

más de 4 años hace | 0

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HDL Coder streaming input instead of vector
Can you share a sample model that explains your usecase?

más de 4 años hace | 0

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HDL Workflow advisor on Intel SoC... Error in Quartus while synthesis: Error (272006): In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Please attach "dut.m" and "testbench.m" file and the HDL Coder project file (.prj) for further analysis and guidance.

más de 4 años hace | 0

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System Generator: HDL Black Box include mem files.
Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are ...

más de 4 años hace | 0

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How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...

más de 4 años hace | 0

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Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...

más de 4 años hace | 0

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HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...

más de 4 años hace | 0

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HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...

más de 4 años hace | 0

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Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...

más de 4 años hace | 0

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How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...

más de 4 años hace | 0

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Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.

más de 4 años hace | 0

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The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.

casi 5 años hace | 0

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Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...

casi 5 años hace | 0

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HDL Coder Buffer Problem
Can you attach the model? Thanks

casi 5 años hace | 0

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Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...

casi 5 años hace | 1

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Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...

casi 5 años hace | 0

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Can SimEvent library components be used with HDL Coder?
HDL Code Generation is supported for SimEvents Blocks. Consider sharing your usecases by reaching out to support@mathworks.com...

casi 5 años hace | 0

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Trenz Electronic TE0820 support in HDL coder toolbox
>> I want to create the algorithm as Simulink models and execute these models in Simulink external mode for debuging and data ga...

casi 5 años hace | 0

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HDL Code Generation Block Support
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code genera...

casi 5 años hace | 0

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Passing HDL parameters through models
This may not yet be supported in HDL block dialogs. Please reach out to support@mathworks.com with your request and usecase mode...

casi 5 años hace | 0

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How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
See the attached file with examples on some of the coding styles. Some of the examples contain FFT variations in MATLAB suitabl...

casi 5 años hace | 0

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VHDL Coder Error: variable-size matrix type is not supported for VHDL code generation
Can you check MALTAB to HDL documentation for examples on how to break the design into dut and testbench files? feel free to att...

casi 5 años hace | 1

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How to convert this simulink model to VHDL ?
Attached a sample model. Please feel free to share your models. What is the exact frequency and is it a constant or variable wi...

casi 5 años hace | 0

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How to build a model using HDL coder library in simulink?
It is quite possible you have installed HDLCoder followed up Xilinx System Generator (XSG) in your machine and some how XSG inst...

casi 5 años hace | 0

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hdl coder work flow adviser block compability error
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection. web(fullfile(docroot, 'h...

casi 5 años hace | 2

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hardware implementation of NN code
Do you have access to these products? https://www.mathworks.com/products/gpu-coder.html GPU Coder™ generates optimized CUDA...

casi 5 años hace | 0

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How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Please share sample MATLAB Code and Testbench and the error you are seeing. Thanks

casi 5 años hace | 0

Respondida
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Can you share a sample code and testbench? See attached example on how to generate HDL from hdl.FFT function.

casi 5 años hace | 0

Respondida
can we generate HDL code for matrix multiplication ?
You can do this to open the models. The models do not use any new 20b features. https://www.mathworks.com/help//simulink/gui/si...

casi 5 años hace | 0

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can we generate HDL code for matrix multiplication ?
Attaching few flavors of matrix multiplication compatible with HDL Coder. matmul_external_memory_20b.slx matmul_mlfb_fixpt_...

alrededor de 5 años hace | 0