System Generator: HDL Black Box include mem files.
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Talon Myburgh
el 23 de Abr. de 2021
Comentada: Talon Myburgh
el 11 de Mayo de 2021
I have successfully managed to wrap up most of my HDL cores in black boxes in Simulink. They can be successfully simulated and synthesized with System Generator. I've done all this using this user guide.
One block I am having issue wrapping up is a FIR filter for which I have specified window coefficients in .mem files for the BRAM's to load. Now, to add all the VHDL source files the black box needs for compilation/simulation, I used the following commands in the black box configuration MATLAB script (see page 186 of the linked document):
addFile("filename");
addFileToLibrary("filename","library");
These commands successfully add VHDL source files to the Vivado project (in the correct library) that System Generator produces. If I try to include a '.mem' file using the above commands however, it does not add it and synthesis down the line will complain that I do not have the required memory files in my Vivado project (obviously).
No where in that linked document is there mention of how to include memory files so I am reaching out to see whether I am missing something or there is a way in which one ought to overcome this hurdle.
PS. I've asked this question in both the Xilinx Community forum and the Xilinx Reddit page but have received no answer as yet... which is why I am asking here.
Thank you.
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Kiran Kintali
el 11 de Mayo de 2021
It looks like it is being addressed here.
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Kiran Kintali
el 11 de Mayo de 2021
(add discussion here)
This is because m-script for sysgen does not recognize the .mem files currently. MEM files were introduced with XPM and this support is missing in sysgen. An enhancement request is filed to support this.
This issue can be worked around by adding the absolute path of the mem file in the HDL generic declaration as well as in the m-script as below
GENERIC(
g_adr_w : NATURAL := 9;
g_dat_w : NATURAL := 22;
g_nof_words : NATURAL := 2**9;
g_rd_latency : NATURAL := 2; -- choose 1 or 2
g_init_file : STRING := "C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_0.mem";
g_ram_primitive : STRING := "auto" --choose auto, distributed, block, ultra
);
this_block.addGeneric('g_init_file','STRING','"C:\sysgenfiles\pfir_coeffs_hanning_t1_p512_b22_wb1_
When the netlist is generated from Sysgen, the code will refer the mem file in the given path and synthesize fine. Only drawback is if the code is ported to other machine or if the file is moved, the mem file location needs to be provided again.
Más respuestas (1)
Kiran Kintali
el 30 de Abr. de 2021
Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are you using?
5 comentarios
Kiran Kintali
el 5 de Mayo de 2021
Thanks for the additional info. Waiting to hear from Xilinx team. No update yet.
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