VHDL Coder Error: variable-size matrix type is not supported for VHDL code generation

Hello,

I ask you to help me to solve the error quoted in the object resulting from the conversion of my MATLAB code to an HDL code for FPGA.

it is noted that the HDL code is correctly generated when I leave default inputs. However, when I select the floating point to fixed point option, I find this error...

Thank you in advance for your time.

function ADH_Function = ADH_Calculator(Text,Tint)
var = coder.const(ADH_Calculator(Text,Tint));
Teds = zeros(1,7);
Tedw = zeros(1,7);
b=1;
Ow = 0;
Own = 0;
Owp = 0;
ps = 0;
pw = 0;
Tc = zeros(1,25);
Trms = zeros(1,25);
Tops = zeros(1,25);  
Trmw = zeros(1,28);
Topw = zeros(1,28);
dhs = zeros(1,2);
dhw = zeros(1,2);
HS = 0;
HW = 0;
%% Summer 
r=1;
for i=4345:168:8209 
        j=i;
        for ks=1:7
        Teds(ks)=(sum(Text(j:j+24))/24); 
        j=j+24;
        end
    Trms(r)=(Teds(1)+Teds(2)*0.8+Teds(3)*0.6+Teds(4)*0.5+Teds(5)*0.4+Teds(6)*0.3+Teds(7)*0.2)/3.8;
	Tops(r)=sum(Tint(i:i+168))/168;
    r=r+1;
end
        j=8377;
        for ks=1:5
        Teds(ks)=(sum(Text(j:j+24))/24);
        j=j+24;
        end
	Trms(r)=(Teds(1)+Teds(2)*0.8+Teds(3)*0.6+Teds(4)*0.5+Teds(5)*0.4)/3.3;
	Tops(r)=sum(Tint(8377:8497))/120;
%%
dhs(1)=0;
dhs(2)=0;
for ps=1:length(Trms)
      Tc(ps)=0.33*Trms(ps)+18.8;
      if (Trms(ps)>10 && Trms(ps)<15)
          if (Tops(ps)>(Tc(ps)+3))
              dhs(1)=dhs(1)+Tops(ps)-(Tc(ps)+3);
          end
      end
      if (Trms(ps)>15 && Trms(ps)<30)
          if (Tops(ps)>(Tc(ps)+3))
              dhs(1)=dhs(1)+Tops(ps)-(Tc(ps)+3);  
          end
          if (Tops(ps)<(Tc(ps)-3))
              dhs(2)=(Tc(ps)-3)-Tops(ps);
          end
      end
end
HS=sum(dhs(:));
%% Winter
l=1;
for v=1:168:4033
        w=v;
        for kw=1:7
        Tedw(kw)=(sum(Text(w:w+24))/24); 
        w=w+24;
        end
   Trmw(l)=(Tedw(1)+Tedw(2)*0.8+Tedw(3)*0.6+Tedw(4)*0.5+Tedw(5)*0.4+Tedw(6)*0.3+Tedw(7)*0.2)/3.8;
   Topw(l)=sum(Tint(v:v+168))/168;
   l=l+1;
end
        w=4200;
        for kw=1:6
        Tedw(kw)=(sum(Text(w:w+24))/24);
        w=w+24;
        end
   Trmw(l)=(Tedw(1)+Tedw(2)*0.8+Tedw(3)*0.6+Tedw(4)*0.5+Tedw(5)*0.4+Tedw(6)*0.3)/3.6;
   Topw(l)=sum(Tint(4200:4344))/144;
   l=l+1;
        w=8497;
        for kw=1:7
        Tedw(kw)=(sum(Text(w:w+24))/24);
        w=w+24;
        end
   Trmw(l)=(Tedw(1)+Tedw(2)*0.8+Tedw(3)*0.6+Tedw(4)*0.5+Tedw(5)*0.4+Tedw(6)*0.3+Tedw(7)*0.2)/3.8;
   Topw(l)=sum(Tint(8497:8665))/168;
   l=l+1;
   
        w=8665;
        for kw=1:4
        Tedw(kw)=(sum(Text(w:w+24))/24);
        w=w+24;
        end
   Trmw(l)=(Tedw(1)+Tedw(2)*0.8+Tedw(3)*0.6+Tedw(4)*0.5)/2.9;
   Topw(l)=sum(Tint(8665:8761))/96;
%%   
  Ow=20;
  dhw(1)=0;
  dhw(2)=0;
  Owp=Ow+3;
  Own=Ow-3;
  for pw=1:length(Topw)
        if (Topw(pw)>Owp)
         dhw(1)=dhw(1)+Topw(pw)-(Owp);
        end
           if (Topw(pw)<Own)
         dhw(2)=dhw(2)+(Own)-Topw(pw);
           end
  end
  HW=sum(dhw(:));
ADH = HS + HW;
ADH_Function = [ADH, HS, HW];

[Rik]

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Answer 1

[Kiran Kintali]

Can you check MALTAB to HDL documentation for examples on how to break the design into dut and testbench files? feel free to attach the two files for additional guidance.

See examples below.

>> mlhdlc_demo_setup('sfir')

>> mlhdlc_demo_setup('heq')

[Dr Badr CHEGARI]

First of all, thank you very much for your answer.

I have checked what you suggested but I still have the same error.

In fact, when I take the same code provided that the variabes (Teds, Trms, Tops... ) are scalars and I launch the conversion, it works without problem, but once I put them back in matrix, it gives this problem.

I tried everything ( variables definition at the beginning,...) but still no favorable answer.

I hope you find something to help me.

[Kiran Kintali]

Can you share the project file and source code used in the project file?

>> hdlcoder

Project file can be created using "hdlcoder" command and a design and testbench. Design gets translated to hardware (VHDL/Verilog) using HDLCoder workflow.d, you need add a design file and a testbench file.

[Dr Badr CHEGARI]

Yes of course, please find enclosed the project file.

Thank you very much for your help!

[Kiran Kintali]

Thanks for sharing the code.

As I expected from the error messages you seem to have too much IO size.

Assuming you use 14bits of fixed-point to represent your range of values you would need 8761*14*2 + 3*14 pins on the core to stream all that data in and out of the chip.

You need to stream the data into the FPGA serially or few samples samples at a time, store it internal RAM (array of persistent variables) do the processing after sufficient data is buffered and passed the outut.

Check histogram equalization example to see how this can be done for images with large framesizes or other examples in MATLAB to HDL workflow.

>> mlhdlc_demo_setup('heq')

[Dr Badr CHEGARI]

Thank you very much for all these informations and for the time you spent solving this problem.

I understand that I have to take into consideration the size of my inputs when implementing the code to the hardware. However, I couldn't find a way to generate the HDL code first, I don't know if you can offer me some syntax suggestions to add to generate the HDL code with fixed points of course. Or it is impossible ?