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Feeds
Delay balancing failed when generating HDL code
It looks like you are hitting a delay balancing error due to latency in a feedback look in the model cannot be matched. https...
1 día hace | 0
simulink can't map matrie to RAM
Hi, Can you please share the model here or reach out to technical support for additional guidance? Thanks
4 días hace | 0
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
13 días hace | 0
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
21 días hace | 0
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
24 días hace | 0
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
24 días hace | 1
| aceptada
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
alrededor de 1 mes hace | 0
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
alrededor de 1 mes hace | 1
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
alrededor de 1 mes hace | 0
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
alrededor de 2 meses hace | 0
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
alrededor de 2 meses hace | 0
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
3 meses hace | 0
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
3 meses hace | 0
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
3 meses hace | 0
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
4 meses hace | 0
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
4 meses hace | 0
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
5 meses hace | 0
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
5 meses hace | 0
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentati...
6 meses hace | 1
Interface with the Deep Learning Processor IP Core (Execution Modes)
System Integration of Deep Learning Processor IP Core This page shows lists the relevant examples https://www.mathworks.com/h...
6 meses hace | 0
| aceptada
Unable to set Synthesis Attribute on Entity using hdlset_param
In the latest release you should see Block and Block Outputs (Signal) related synthesis attributes specification dialogs and t...
7 meses hace | 0
Unable to set Synthesis Attribute on Entity using hdlset_param
https://www.mathworks.com/help/hdlcoder/ug/configure-custom-synthesis-attributes-for-simulink-blocks.html HDL Coder allows at...
7 meses hace | 0
Deep Learning HDL Toolbox with CycloneV SoC board
Can you consider using the example and extend to DE-10 Nao Kit? https://www.mathworks.com/help/hdlcoder/ug/define-and-register-...
7 meses hace | 0
Convert a part of simulink model of my project to VHDL or Verilog code for FPGA
https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html Simscape Hardware-in-the-Loop Workflow Generate HDL code from S...
9 meses hace | 0
Is it possible to change Simulink MATLAB Function Block 1-indexing to 0-indexing?
If possible can you share your model and the version of MATLAB you are using? There are few tricks in MATLAB coding and design...
9 meses hace | 0
| aceptada
Dose HDL coder generate Verilog HDL-1995 verision or Verilog HDL-2001 version？
HDL Coder Language Support VHDL, Verilog, and SystemC HLS Language Support The generated HDL code complies with the following...
9 meses hace | 1
When I click on "View Code" after generating Verilog code in HDL Coder, the program doesn't respond.
https://www.mathworks.com/help/hdlcoder/ug/traceability-report.html If you are facing issues with code view please reach out to...
9 meses hace | 0
| aceptada
HDL Code Generation Issue – Exceeding IO Pin Count Threshold & MATLAB Freezing
If the generated HDL DUT code results in unreasonable IO, it may eventually lead to failure to meet pin constraint during synthe...
9 meses hace | 0
SigmoidLayer wont work while implementing on ZC706
Thank you for reporting this. Development team is able to reproduce the issue and will post an update soon.
10 meses hace | 0
Simulink HDL Coder error when generating
This is an unexpected error handling the if/elseif control structure. Please reach to tech support or share your model here. We ...
10 meses hace | 0
