DO-178C Workflow for Automatic Test Vector Generation - MATLAB & Simulink
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    DO-178C Workflow for Automatic Test Vector Generation

    Model coverage analysis can be a manual, tedious process. If you have missing model coverage, it can be difficult to know how to exercise the model to understand whether you have an incomplete test suite, missing requirements, or design errors.

    In this video, you will learn how to use Simulink Design Verifier to automatically generate test vectors to analyze missing model coverage collected by Simulink Coverage in order to comply with DO-178C and its supplements.

    Published: 13 Jan 2020

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