QPSK Modulator Baseband

Modulate using quadrature phase shift keying method

• 

Libraries:
Communications Toolbox / Modulation / Digital Baseband Modulation / PSK
Communications Toolbox HDL Support / Modulation / PM

Description

The QPSK Modulator Baseband block modulates signals using the quadrature phase shift keying (QPSK) method. The output is a baseband representation of the modulated signal. This block accepts a scalar or column vector input signal. For information about the data types, see Supported Data Types.

Examples

Plot Noisy QPSK Constellation

Apply QPSK modulation to a signal of random data. Pass the modulated signal through an additive white Gaussian noise (AWGN) channel. Plot the signal constellation.

The doc_qpsk_mod model generates QPSK data, applies the AWGN, and displays the resulting constellation diagram.

Run the model with the Eb/N0 of the AWGN Channel block set to 15 dB. The constellation diagram shows the QPSK symbol samples with AWGN.

Change the Eb/N0 from 15 dB to 10 dB. The noise level increases as shown by the greater distance between the samples in the constellation diagram.

Demodulate Noisy QPSK Signal

Modulate and demodulate a noisy QPSK signal.

The doc_qpsk_demod model QPSK-modulates random frames of binary data, adds noise to the modulated data, QPSK-demodulates the data, and then calculates the error rate of the received signal.

Running the simulation saves error rate results to the base workspace in the 1-by-3 row vector, ErrorVec. The first element holds the bit error rate (BER).

The AWGN Channel block has Eb/N0 set to 4.3 dB. Run the model to display the error statistics. For an Eb/N0 of 4.3 dB, the resultant BER is approximately 0.01. Your results might vary slightly.

ans =

    0.0104

Increase Eb/N0 for the AWGN to 7 dB. Rerun the simulation, and observe that the BER has decreased.

ans =

   7.0000e-04

Compare Filtered QPSK and MSK Signals in Simulink

The cm_qpsk_vs_msk model compares filtered quadrature phase shift keying (QPSK) and minimum shift keying (MSK) modulation schemes.

The model generates the filtered QPSK signal using random integer data from the Random Integer Generator block, which gets modulated by the QPSK Modulator Baseband block, and then filtered by the Raised Cosine Transmit Filter block. The model generates the MSK signal using random binary data from the Bernoulli Binary Generator block, which gets modulated by the MSK Modulator Baseband block. The model adds noise to both the filtered QPSK and MSK signals by using AWGN Channel blocks. The Eye Diagram blocks are used to visualize eye diagrams of both signals.

For filtered QPSK modulation, the values of both the in-phase and quadrature components of the signal are permitted to change at any symbol interval. For MSK modulation, the symbol interval is half that for QPSK, but the in-phase and quadrature components change values in alternate symbol epochs.

Compare eye diagram plots of a QPSK-modulated signal and an MSK-modulated signal. For QPSK, the ideal sampling period is 1/2 sample, with sampling time for both in-phase and quadrature signal components at 0.5, 1.5, 2.5, .... For MSK, the ideal sample period is 1 sample, with sampling time at 0.5, 1.5, 2.5, ... for the in-phase signal component and 1, 2, 3, ... for the quadrature signal component.

Ports

Input

In — Input signal

scalar | column vector

Input signal, specified as a scalar or column vector.

• When you set Input type to Integer, specify the input signal elements as integers in the range [0, 3].

• When you set Input type to Bit, specify the input signal as a binary vector containing an even number of elements to ensure a whole number of the 2-bit QPSK modulation symbols.

This port in unnamed on the block.

Data Types: double | single | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Output

Out — QPSK-modulated baseband signal

scalar | vector

QPSK-modulated baseband signal, returned as a complex-valued scalar or vector. The output is the complex baseband representation of the QPSK-modulated signal.

This port in unnamed on the block.

Data Types: double | single | fixed point

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Main

Input type — Integer or bit pair input indicator

Integer (default) | Bit

Integer or bit pair input indicator, specified as Integer or Bit.

Constellation ordering — Symbol mapping

Gray (default) | Binary

Symbol mapping of integer or bit pair inputs, specified as Gray or Binary.

• To map symbols using Gray-coded ordering, set this parameter to Gray.

• To map symbols using binary-coded ordering, set this parameter to Binary.

For more information, see Integer-Valued Signals and Binary-Valued Signals.

Phase offset (rad) — Phase offset of zeroth point

pi/4 (default) | scalar

Phase of the zeroth point of the signal constellation in radians, specified as a scalar.

View constellation — Option to plot reference constellation

button

Click View Constellation on the block mask to visualize a signal constellation for the specified block parameters. Before viewing a constellation, apply the parameter settings. For more information, see View Constellation of Modulator Block.

Data Types

Output data type — Output data type

double (default) | single | fixdt(1,16) | fixdt(1,16,0) | Inherit via back propagation | <data type expression>

Output data type, specified as double, single, fixdt(1,16), fixdt(1,16,0), Inherit via back propagation, or <data type expression>.

• fixdt(1,16), fixdt(1,16,0), or <data type expression> enables parameters in which you can further specify details.

• Inherit via back propagation sets the output data type and scaling to match the following block.

For information about specifying data types, see Data Type Assistant.

Block Characteristics

Data Types	Boolean | double | fixed pointa, b | integer | single
Multidimensional Signals	no
Variable-Size Signals	yes
a ufix(1) at the input if ''input type'' is set to ''bit''. ufix(ceil(log2(M))) at input if ''input type'' is set to ''integer'' for M-ary modulation. b Fixed-point outputs must be signed.

More About

Integer-Valued Signals and Binary-Valued Signals

If you set the Input type parameter to Integer, then valid input values are 0, 1, 2, and 3. When you set Constellation ordering to Binary for input m the output symbol is e^{(jθ + jπm/2)}, where θ represents the Phase offset parameter. In this case, the block accepts a scalar or column vector signal.

If you set the Input type parameter to Bit, then the input contains pairs of binary values. For this configuration, the block accepts column vectors with even lengths. When you set the Phase offset parameter to π/4, then the block uses one of the signal constellations in this figure, depending on whether you set the Constellation ordering parameter to Binary or Gray. In this figure, the most significant bit is the left-most bit and is the first bit input to the block.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Boolean when Input type is Bit 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers ufix(1) when Input type is Bit ufix(2) when Input type is Integer
Output	Double-precision floating point Single-precision floating point Signed fixed point

Data Type Assistant

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant (Simulink).

Algorithms

In quadrature phase shift keying, the message bits are grouped into 2-bit symbols, which are transmitted as one of four phases of a constant amplitude baseband signal. This grouping provides a bandwidth efficiency that is twice as great as the efficiency of BPSK. The general QPSK signal is expressed as

$$s_m(t)=\sqrt{\frac{2E_s}{T_s}}\cos \left(2\pi f_{c}t+\frac{2\pi m}{4}+\varphi \right);m\in \{0,1,2,3\},$$

where E_s is the energy per symbol, T_s is the symbol duration, and ϕ is the initial phase offset. The complex baseband representation of a QPSK signal is

$$s_m(t)=\exp \left(j\left(\frac{2\pi m}{4}+\varphi \right)\right);m\in \{0,1,2,3\}.$$

In this QPSK constellation diagram, each 2-bit sequence is mapped to one of four possible states. The states correspond to phases of π/4, 3π/4, 5π/4, and 7π/4.

To improve bit error rate performance, you can map the incoming bits to a Gray-coded ordering. The primary advantage of the Gray code is that only one of the two bits changes when moving between adjacent constellation points. This table compares constellation point sequences for binary and Gray mapping.

Binary-Coded Sequence	Gray-Coded Sequence
00	00
01	01
10	11
11	10

You can apply Gray codes to higher-order modulations, as shown in this Gray-coded QPSK constellation.

The bit error probability for QPSK in AWGN with Gray coding is

$$P_b=Q\left(\sqrt{\frac{2E_b}{N_0}}\right),$$

which is the same as the expression for BPSK. As a result, QPSK provides the same performance with twice the bandwidth efficiency.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a