Clocking and Multirate Design
Timing Controller and Clocks
Reset and Clock Enable
- Generate a Global Oversampling Clock
In many designs, the DUT is not self-contained.
- Code Generation from Multirate Models
Overview of HDL code generation for single-clock, single-tasking multirate models.
- Multirate Model Requirements for HDL Code Generation
Guidelines for setting up multirate models and blocks for HDL code generation.
- Timing Controller for Multirate Models
A timing controller entity generates the required rates from a single primary clock, using one or more counters to create multiple clock enables.
- Generate Reset for Timing Controller
How to generate reset for timing controller.
- Using Triggered Subsystems for HDL Code Generation
How to use Triggered Subsystems, Trigger As Clock property, and generate HDL code.