In many designs, the DUT is not self-contained.
Overview of HDL code generation for single-clock, single-tasking multirate models
Guidelines for setting up multirate models and blocks for HDL code generation.
A timing controller entity generates the required rates from a single master clock, using one or more counters to create multiple clock enables.
How to generate reset for timing controller.
How to use Triggered Subsystems, Trigger As Clock property, and generate HDL code.