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addAXI4SlaveInterface

Class: hdlcoder.ReferenceDesign
Package: hdlcoder

Add and define AXI4 slave interface

Syntax

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,Name,Value)
addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value)

Description

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr) adds and defines an AXI4 interface for an Altera® reference design, or an AXI4 or AXI4-Lite interface for a Xilinx® ISE reference design.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado® reference designs.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,Name,Value) adds and defines an AXI4 interface for an Altera reference design, or an AXI4 or AXI4-Lite interface for a Xilinx ISE reference design, with additional options specified by one or more Name,Value pair arguments.

addAXI4SlaveInterface('InterfaceConnection',ref_design_port,'BaseAddress',base_addr,'MasterAddressSpace',master_addr_space,Name,Value) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado reference designs, with additional options specified by one or more Name,Value pair arguments.

Input Arguments

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Reference design port that is connected to the AXI4 or AXI4-Lite interface, specified as a character vector. For reference designs based on Intel® Qsys™, when you want to connect multiple AXI Master IPs to the AXI4 or AXI4-Lite interface, specify each of the AXI Master instance names and the corresponding port names as a cell array of character vectors.

Example: 'axi_interconnect_0/M00_AXI', {'hps_0.h2f_axi_master','master_0.master'},...

Base address for AXI4 or AXI4-Lite slave interface, specified as a character vector.

Example: '0x40010000'

Address space of the master interface connected to this slave interface, specified as a character vector. For Vivado reference designs only. When you want to connect more than one AXI Master IP, specify each of the AXI Master instance names and the corresponding address spaces.

Example: 'processing_system7_0/Data', {'processing_system7_0/Data','hdlverifier_axi_master_0/axi4m'}

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Type of interface connection, specified as a character vector or a cell array of character vectors.

Example: 'InterfaceType','AXI4-Lite' specifies an 'AXI4–Lite' interface type connection.

Name of the interface, specified as a character vector. When you provide the InterfaceID, InterfaceType must be set to either 'AXI4' or 'AXI4–Lite'.

Example: 'InterfaceID','MyAXI4','InterfaceType','AXI4' specifies interface name as 'MyAXI4' and interface type as 'AXI4'.

Width of all ID signals, such as AWID, WID, ARID, and RID, specified as a positive integer. This property enables you to specify the number of AXI Master interfaces that you want the AXI4 slave interface in the HDL DUT IP core to connect to. The default value is 12, which enables you to connect the HDL IP core to one AXI Master interface. To connect the IP core to multiple AXI Master interfaces, increase the IDWidth. The ID width is tool-specific.

Example: 'IDWidth','13' may indicate that you want the IP core to connect to two AXI Master interfaces in the reference design.

Tips

Introduced in R2015a