hdlcoder.WorkflowConfig

R2026b

Configure HDL code generation and deployment workflows

Description

An hdlcoder.WorkflowConfig object stores HDL workflow configuration options. Use the hdlcoder.WorkflowConfig object with the hdlcoder.runWorkflow function to run HDL code generation and deployment workflows.

Creation

Syntax

hWC = hdlcoder.WorkflowConfig(Name=Value)

Description

hWC = hdlcoder.WorkflowConfig(Name=Value) creates an hdlcoder.WorkflowConfig object for you to specify your HDL code generation and deployment workflows, with additional options specified by one or more Name=Value arguments. You can customize the hdlcoder.WorkflowConfig object for these workflows:

Generic ASIC/FPGA
FPGA-in-the-Loop (requires SoC Blockset™ for AMD)
IP Core Generation
Simulink Real-Time FPGA I/O (requires Simulink^® Real-Time™)

example

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Example: SynthesisTool="Xilinx Vivado"

`SynthesisTool` — Synthesis tool name
`"Xilinx Vivado"` (default) | `"Altera QUARTUS II"` | `"Xilinx ISE"` | `"Microchip Libero SoC"` | `"Cadence Genus"` | `"Synplify Elite"`

Name of the synthesis tool, specified as a character vector.

Example: hdlcoder.WorkflowConfig(SynthesisTool="Altera QUARTUS II") creates an hdlcoder.WorkflowConfig object with "Altera QUARTUS II" as the synthesis tool and "Generic ASIC/FPGA" as the target workflow.

`TargetWorkflow` — Specify the target workflow
`"Generic ASIC/FPGA"` (default) | `"IP Core Generation"` | `"FPGA-in-the-Loop"` | `"Simulink Real-Time FPGA I/O"`

Target workflow for HDL code generation, specified as a character vector.

Example: hdlcoder.WorkflowConfig(TargetWorkflow="IP Core Generation") creates an hdlcoder.WorkflowConfig object with "Xilinx Vivado" as the synthesis tool and "IP Core Generation" as the target workflow.

Output Arguments

expand all

`hWC` — Workflow configuration object
`hdlcoder.WorkflowConfig` object

Workflow configuration object, returned as an hdlcoder.WorkflowConfig object. Use this object to configure HDL code generation and deployment workflows for the hdlcoder.runWorkflow function.

Properties

HDL Workflow Configuration Properties

Configure HDL code generation and deployment workflows

Object Functions

`export`	Generate script that recreates the workflow configuration
`setAllTasks`	Enable all tasks in workflow
`clearAllTasks`	Disable all tasks in workflow
`validate`	Check property values in HDL workflow configuration object

Examples

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Configure and Run Generic ASIC/FPGA Workflow with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a generic ASIC/FPGA workflow script that targets an AMD^® Virtex^® 7 device and uses the AMD Vivado^® synthesis tool.

Open and view your exported HDL workflow script.

% Export Workflow Configuration Script
% Generated with MATLAB 9.5 (R2018b Prerelease) at 14:42:37 on 29/03/2018
% This script was generated using the following parameter values:
%     Filename  : "S:\generic_workflow_example.m"
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : "sfir_fixed/symmetric_fir"
% To view changes after modifying the workflow, run the following command:
% >> export(hWC,DUT='sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system("sfir_fixed");

%% Restore the Model to default HDL parameters
%hdlrestoreparams("sfir_fixed/symmetric_fir");

%% Model HDL Parameters
%% Set Model "sfir_fixed" HDL parameters
hdlset_param("sfir_fixed", "GenerateCoSimModel", "ModelSim");
hdlset_param("sfir_fixed", "GenerateHDLTestBench", "off");
hdlset_param("sfir_fixed", "HDLSubsystem", "sfir_fixed/symmetric_fir");
hdlset_param("sfir_fixed", "SynthesisTool", "Xilinx Vivado");
hdlset_param("sfir_fixed", "SynthesisToolChipFamily", "Virtex7");
hdlset_param("sfir_fixed", "SynthesisToolDeviceName", "xc7vx485t");
hdlset_param("sfir_fixed", "SynthesisToolPackageName", "ffg1761");
hdlset_param("sfir_fixed", "SynthesisToolSpeedValue", "-2");
hdlset_param("sfir_fixed", "TargetDirectory", "hdl_prj\hdlsrc");


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig(SynthesisTool="Xilinx Vivado",TargetWorkflow="Generic ASIC/FPGA");

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

%Set Properties related to synthesis tool version
hWC.AllowUnsupportedToolVersion  = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.RunTaskVerifyWithHDLCosimulation = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskRunSynthesis = true;
hWC.RunTaskRunImplementation = false;
hWC.RunTaskAnnotateModelWithSynthesisResult = true;

% Set properties related to "RunTaskGenerateRTLCodeAndTestbench" Task
hWC.GenerateRTLCode = true;
hWC.GenerateTestbench = false;
hWC.GenerateValidationModel = false;

% Set properties related to "RunTaskCreateProject" Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';

% Set properties related to "RunTaskRunSynthesis" Task
hWC.SkipPreRouteTimingAnalysis = false;

% Set properties related to "RunTaskRunImplementation" Task
hWC.IgnorePlaceAndRouteErrors = false;

% Set properties related to "RunTaskAnnotateModelWithSynthesisResult" Task
hWC.CriticalPathSource = 'pre-route';
hWC.CriticalPathNumber =  1;
hWC.AnnotateModel = "original";
hWC.ShowAllPaths = false;
hWC.ShowDelayData = true;
hWC.ShowUniquePaths = false;
hWC.ShowEndsOnly = false;

% Validate the Workflow Configuration Object
validate(hWC);

%% Run the workflow
hdlcoder.runWorkflow("sfir_fixed/symmetric_fir", hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is generic_workflow_example.m, at the command line, enter:

generic_workflow_example

Configure and Run FPGA-in-the-Loop with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is an FPGA-in-the-Loop workflow script that targets an AMD Virtex 5 development board and uses the AMD ISE synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB R2026a at 15:11:23 on 04/05/2025
% This script was generated using the following parameter values:
%     Filename  : "C:\work\hdl_prj\hdlworkflow_FIL.m"
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : "sfir_fixed/symmetric_fir"
% To view changes after modifying the workflow, run the following command:
% >> export(hWC,DUT='sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system("sfir_fixed");

%% Restore the Model to default HDL parameters
%hdlrestoreparams("sfir_fixed/symmetric_fir");

%% Model HDL Parameters
%% Set Model "sfir_fixed" HDL parameters
hdlset_param("sfir_fixed", "HDLSubsystem", "sfir_fixed/symmetric_fir");
hdlset_param("sfir_fixed", "SynthesisTool", "Xilinx Vivado");
hdlset_param("sfir_fixed", "SynthesisToolChipFamily", "Kintex7");
hdlset_param("sfir_fixed", "SynthesisToolDeviceName", "xc7k325t");
hdlset_param("sfir_fixed", "SynthesisToolPackageName", "ffg900");
hdlset_param("sfir_fixed", "SynthesisToolSpeedValue", "-2");
hdlset_param("sfir_fixed", "TargetDirectory", "hdl_prj\hdlsrc");
hdlset_param("sfir_fixed", "TargetFrequency", 25);
hdlset_param("sfir_fixed", "TargetPlatform", "Xilinx Kintex-7 KC705 development board");
hdlset_param("sfir_fixed", "Workflow", "FPGA-in-the-Loop");


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig(SynthesisTool="Xilinx Vivado",TargetWorkflow="FPGA-in-the-Loop");

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

%Set Properties related to synthesis tool version
hWC.AllowUnsupportedToolVersion  = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.RunTaskVerifyWithHDLCosimulation = false;
hWC.RunTaskBuildFPGAInTheLoop = true;

% Set properties related to "RunTaskGenerateRTLCodeAndTestbench" Task
hWC.GenerateRTLCode = true;
hWC.GenerateTestbench = false;
hWC.GenerateValidationModel = false;

% Set properties related to "RunTaskBuildFPGAInTheLoop" Task
hWC.IPAddress = '192.168.0.2';
hWC.MACAddress = '00-0A-35-02-21-8A';
hWC.SourceFiles = "";
hWC.Connection = 'Ethernet';
hWC.RunExternalBuild = true;

% Validate the Workflow Configuration Object
validate(hWC);

%% Run the workflow
hdlcoder.runWorkflow("sfir_fixed/symmetric_fir", hWC);
hdlcoder.runWorkflow("hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA", hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is FIL_workflow_example.m, at the command line, enter:

fil_workflow_example

Configure and Run IP Core Generation Workflow with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is an IP core generation workflow script that targets the Altera^® Cyclone^® V SoC development kit and uses the Altera Quartus^® II synthesis tool.

Open and view your exported HDL workflow script.

% Export Workflow Configuration Script
% Generated with MATLAB 8.6 (R2015b) at 14:42:16 on 08/07/2015
% Parameter Values:
%     Filename  : "S:\ip_core_gen_workflow_example.m"
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : "hdlcoder_led_blinking/led_counter"

%% Load the Model
load_system("hdlcoder_led_blinking");

%% Model HDL Parameters
% Set Model HDL parameters
hdlset_param("hdlcoder_led_blinking", ...
    "HDLSubsystem", "hdlcoder_led_blinking/led_counter");
hdlset_param("hdlcoder_led_blinking", "OptimizationReport", "on");
hdlset_param("hdlcoder_led_blinking", ...
    "ReferenceDesign", "Default system (Qsys 14.0)");
hdlset_param("hdlcoder_led_blinking", "ResetType", "Synchronous");
hdlset_param("hdlcoder_led_blinking", "ResourceReport", "on");
hdlset_param("hdlcoder_led_blinking", "SynthesisTool", "Altera QUARTUS II");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolChipFamily", "Cyclone V");
hdlset_param("hdlcoder_led_blinking", "SynthesisToolDeviceName", "5CSXFC6D6F31C6");
hdlset_param("hdlcoder_led_blinking", "TargetDirectory", "hdl_prj\hdlsrc");
hdlset_param("hdlcoder_led_blinking", ...
    "TargetPlatform", "Altera Cyclone V SoC development kit - Rev.D");
hdlset_param("hdlcoder_led_blinking", "Traceability", "on");
hdlset_param("hdlcoder_led_blinking", "Workflow", "IP Core Generation");

% Set SubSystem HDL parameters
hdlset_param("hdlcoder_led_blinking/led_counter", ...
    "ProcessorFPGASynchronization", "Free running");

% Set Inport HDL parameters
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_frequency", ...
    "IOInterface", "AXI4");
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_frequency", ...
    "IOInterfaceMapping", "x""100""");
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_frequency", ...
    "IOInterfaceOptions", {"RegisterInitialValue", 5});

% Set Inport HDL parameters
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_direction", ...
    "IOInterface", "AXI4");
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_direction", ...
    "IOInterfaceMapping", "x""104""");
hdlset_param("hdlcoder_led_blinking/led_counter/Blink_direction", ...
    "IOInterfaceOptions", {"RegisterInitialValue", 1});

% Set Outport HDL parameters
hdlset_param("hdlcoder_led_blinking/led_counter/LED", "IOInterface", "External Port");

% Set Outport HDL parameters
hdlset_param("hdlcoder_led_blinking/led_counter/Read_back", "IOInterface", "AXI4");
hdlset_param("hdlcoder_led_blinking/led_counter/Read_back", ...
    "IOInterfaceMapping", "x""108""");
hdlset_param("hdlcoder_led_blinking/led_counter/Read_back", ...
    "IOInterfaceOptions", {"RegisterInitialValue", 3});

%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig(SynthesisTool="Altera QUARTUS II", ...
    TargetWorkflow="IP Core Generation");

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';

%Set Properties related to synthesis tool version
hWC.AllowUnsupportedToolVersion  = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskGenerateSoftwareInterface = false;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskProgramTargetDevice = false;

% Set Properties related to Generate RTL Code And IP Core Task
hWC.GenerateIPCoreReport = true;

% Set Properties related to Create Project Task
hWC.Objective = hdlcoder.Objective.AreaOptimized;

% Set Properties related to Generate Software Interface Model Task
hWC.OperatingSystem = '';
hWC.AddLinuxDeviceDriver = false;

% Set Properties related to Build FPGA Bitstream Task
hWC.RunExternalBuild = true;
hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;

% Validate the Workflow Configuration Object
validate(hWC);

%% Run the workflow
hdlcoder.runWorkflow("hdlcoder_led_blinking/led_counter", hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is ip_core_workflow_example.m, at the command line, enter:

ip_core_gen_workflow_example

Configure and Run Simulink Real-Time FPGA I/O Workflow for ISE-Based Boards with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a Simulink Real-Time FPGA I/O workflow script that targets the Speedgoat IO331 board that uses the AMD ISE synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB R2026a at 18:14:14 on 08/05/2025
% This script was generated using the following parameter values:
%     Filename  : "C:\work\hdl_prj\hdlworkflow_IO331.m"
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : "sfir_fixed/symmetric_fir"
% To view changes after modifying the workflow, run the following command:
% >> export(hWC,DUT='sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system("sfir_fixed");

%% Restore the Model to default HDL parameters
%hdlrestoreparams("sfir_fixed/symmetric_fir");

%% Model HDL Parameters
%% Set Model "sfir_fixed" HDL parameters
hdlset_param("sfir_fixed", "HDLSubsystem", "sfir_fixed/symmetric_fir");
hdlset_param("sfir_fixed", "SynthesisTool", "Xilinx ISE");
hdlset_param("sfir_fixed", "SynthesisToolChipFamily", "Spartan6");
hdlset_param("sfir_fixed", "SynthesisToolDeviceName", "xc6slx150");
hdlset_param("sfir_fixed", "SynthesisToolPackageName", "fgg676");
hdlset_param("sfir_fixed", "SynthesisToolSpeedValue", "-3");
hdlset_param("sfir_fixed", "TargetDirectory", "hdl_prj\hdlsrc");
hdlset_param("sfir_fixed", "TargetFrequency", 75);
hdlset_param("sfir_fixed", "TargetPlatform", "Speedgoat IO331");
hdlset_param("sfir_fixed", "Workflow", "Simulink Real-Time FPGA I/O");


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig(SynthesisTool="Xilinx ISE",TargetWorkflow="Simulink Real-Time FPGA I/O");

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';
hWC.ReferenceDesignToolVersion = '';
hWC.IgnoreToolVersionMismatch = false;

%Set Properties related to synthesis tool version
hWC.AllowUnsupportedToolVersion  = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCode = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskPerformLogicSynthesis = true;
hWC.RunTaskPerformMapping = true;
hWC.RunTaskPerformPlaceAndRoute = true;
hWC.RunTaskGenerateProgrammingFile = true;
hWC.RunTaskGenerateSimulinkRealTimeInterface = true;

% Set properties related to "RunTaskCreateProject" Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';

% Set properties related to "RunTaskPerformMapping" Task
hWC.SkipPreRouteTimingAnalysis = true;

% Set properties related to "RunTaskPerformPlaceAndRoute" Task
hWC.IgnorePlaceAndRouteErrors = false;

% Validate the Workflow Configuration Object
validate(hWC);

%% Run the workflow
hdlcoder.runWorkflow("sfir_fixed/symmetric_fir", hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is slrt_workflow_example.m, at the command line, enter:

slrt_workflow_example

Configure and Run Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards with a Script

This example shows how to configure and run an exported HDL workflow script.

To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a Simulink Real-Time FPGA I/O workflow script that targets the Speedgoat IO333-325K board that uses the AMD Vivado synthesis tool.

Open and view your exported HDL workflow script.

%--------------------------------------------------------------------------
% HDL Workflow Script
% Generated with MATLAB R2026a at 18:14:33 on 08/05/2025
% This script was generated using the following parameter values:
%     Filename  : "C:\work\hdl_prj\hdlworkflow_IO333.m"
%     Overwrite : true
%     Comments  : true
%     Headers   : true
%     DUT       : "sfir_fixed/symmetric_fir"
% To view changes after modifying the workflow, run the following command:
% >> export(hWC,DUT='sfir_fixed/symmetric_fir');
%--------------------------------------------------------------------------

%% Load the Model
load_system("sfir_fixed");

%% Restore the Model to default HDL parameters
%hdlrestoreparams("sfir_fixed/symmetric_fir");

%% Model HDL Parameters
%% Set Model "sfir_fixed" HDL parameters
hdlset_param("sfir_fixed", "HDLSubsystem", "sfir_fixed/symmetric_fir");
hdlset_param("sfir_fixed", "SynthesisTool", "Xilinx Vivado");
hdlset_param("sfir_fixed", "SynthesisToolChipFamily", "Kintex7");
hdlset_param("sfir_fixed", "SynthesisToolDeviceName", "xc7k325t");
hdlset_param("sfir_fixed", "SynthesisToolPackageName", "ffg900");
hdlset_param("sfir_fixed", "SynthesisToolSpeedValue", "-2");
hdlset_param("sfir_fixed", "TargetDirectory", "hdl_prj\hdlsrc");
hdlset_param("sfir_fixed", "TargetFrequency", 100);
hdlset_param("sfir_fixed", "TargetPlatform", "Speedgoat IO333-325K");
hdlset_param("sfir_fixed", "Workflow", "Simulink Real-Time FPGA I/O");


%% Workflow Configuration Settings
% Construct the Workflow Configuration Object with default settings
hWC = hdlcoder.WorkflowConfig(SynthesisTool="Xilinx Vivado",TargetWorkflow="Simulink Real-Time FPGA I/O");

% Specify the top level project directory
hWC.ProjectFolder = 'hdl_prj';
hWC.ReferenceDesignToolVersion = '2017.4';
hWC.IgnoreToolVersionMismatch = false;

%Set Properties related to synthesis tool version
hWC.AllowUnsupportedToolVersion  = true;

% Set Workflow tasks to run
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskGenerateSimulinkRealTimeInterface = true;

% Set properties related to "RunTaskGenerateRTLCodeAndIPCore" Task
hWC.GenerateIPCoreReport = true;
hWC.GenerateIPCoreTestbench = false;
hWC.CustomIPTopHDLFile = "";
hWC.AXI4RegisterReadback = false;
hWC.IPDataCaptureBufferSize = "128";

% Set properties related to "RunTaskCreateProject" Task
hWC.Objective = hdlcoder.Objective.None;
hWC.AdditionalProjectCreationTclFiles = '';
hWC.EnableIPCaching = true;

% Set properties related to "RunTaskBuildFPGABitstream" Task
hWC.RunExternalBuild = false;
hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default;
hWC.CustomBuildTclFile = '';
hWC.ReportTimingFailure = hdlcoder.ReportTiming.Error;

% Validate the Workflow Configuration Object
validate(hWC);

%% Run the workflow
hdlcoder.runWorkflow("sfir_fixed/symmetric_fir", hWC);

Optionally, edit the script.

For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.

Run the HDL workflow script.

For example, if the script file name is slrt_workflow_example.m, at the command line, enter:

slrt_workflow_example

Tips

A best practice is to use the HDL Workflow Advisor to configure the workflow, and then export a workflow script. The commands in the workflow script create and configure the hdlcoder.WorkflowConfig object. In the HDL Workflow Advisor, select File > Export to Script. See Run HDL Workflow with a Script.
When using the IP Core Generation workflow from the Simulink Toolstrip, you can export workflow settings to a script from the HDL Code tab. In the HDL Code tab, select Share > Export HDL Workflow to Script. For more information on using the IP Core Generation workflow with the Simulink Toolstrip, see Comparison of IP Core Deployment and Verification Techniques.

Version History

Introduced in R2015b

hdlcoder.WorkflowConfig

Description

Creation

Syntax

Description

Name-Value Arguments

`SynthesisTool` — Synthesis tool name
`"Xilinx Vivado"` (default) | `"Altera QUARTUS II"` | `"Xilinx ISE"` | `"Microchip Libero SoC"` | `"Cadence Genus"` | `"Synplify Elite"`

`TargetWorkflow` — Specify the target workflow
`"Generic ASIC/FPGA"` (default) | `"IP Core Generation"` | `"FPGA-in-the-Loop"` | `"Simulink Real-Time FPGA I/O"`

Output Arguments

`hWC` — Workflow configuration object
`hdlcoder.WorkflowConfig` object

Properties

Object Functions

Examples

Configure and Run Generic ASIC/FPGA Workflow with a Script

Configure and Run FPGA-in-the-Loop with a Script

Configure and Run IP Core Generation Workflow with a Script

Configure and Run Simulink Real-Time FPGA I/O Workflow for ISE-Based Boards with a Script

Configure and Run Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards with a Script

Tips

Version History

See Also

Functions

Properties

Topics

hdlcoder.WorkflowConfig

Description

Creation

Syntax

Description

Name-Value Arguments

SynthesisTool — Synthesis tool name "Xilinx Vivado" (default) | "Altera QUARTUS II" | "Xilinx ISE" | "Microchip Libero SoC" | "Cadence Genus" | "Synplify Elite"

TargetWorkflow — Specify the target workflow "Generic ASIC/FPGA" (default) | "IP Core Generation" | "FPGA-in-the-Loop" | "Simulink Real-Time FPGA I/O"

Output Arguments

hWC — Workflow configuration object hdlcoder.WorkflowConfig object

Properties

Object Functions

Examples

Configure and Run Generic ASIC/FPGA Workflow with a Script

Configure and Run FPGA-in-the-Loop with a Script

Configure and Run IP Core Generation Workflow with a Script

Configure and Run Simulink Real-Time FPGA I/O Workflow for ISE-Based Boards with a Script

Configure and Run Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards with a Script

Tips

Version History

See Also

Functions

Properties

Topics

`SynthesisTool` — Synthesis tool name
`"Xilinx Vivado"` (default) | `"Altera QUARTUS II"` | `"Xilinx ISE"` | `"Microchip Libero SoC"` | `"Cadence Genus"` | `"Synplify Elite"`

`TargetWorkflow` — Specify the target workflow
`"Generic ASIC/FPGA"` (default) | `"IP Core Generation"` | `"FPGA-in-the-Loop"` | `"Simulink Real-Time FPGA I/O"`

`hWC` — Workflow configuration object
`hdlcoder.WorkflowConfig` object