Guidelines for Speed and Area Optimizations
The HDL modeling guidelines are a set of recommended guidelines for creating Simulink® models, MATLAB Function blocks, and Stateflow® charts for code generation with HDL Coder™. In addition to providing architectural guidance, because the generated code targets hardware platforms such as FPGAs, ASICs, and SoCs, you can use these guidelines to optimize your design for speed or area on the target hardware.
List of Guidelines and Severity Levels
List of speed and area optimization guidelines in ascending order of Guideline ID.
Various severity levels associated with the HDL modeling guidelines and their description.
Guidelines for Area Optimizations
Recommended settings for using the resource sharing optimization effectively for various blocks.
Recommended settings for using the resource sharing optimization effectively for Subsystems and floating-point IPs.
Resource sharing is an area optimization in which HDL Coder identifies multiple functionally equivalent resources and replaces them with a single resource.
Guidelines for Speed Optimizations
The code generator introduces registers when you specify certain block implementations or use certain settings.
Recommended settings for using the distributed pipelining optimization effectively with vector inputs.