Certain patterns or combination of blocks with registers can improve the achievable clock frequency and reduce the area usage on the FPGA boards. The adaptive pipelining optimization creates these patterns by inserting pipeline registers to the blocks in your design. To determine the optimal number of pipeline registers to insert in your design, the optimization considers the target device, target frequency, multiplier word lengths, and the settings in the HDL Block Properties. See Adaptive Pipelining.
By default, the adaptive pipelining optimization is disabled on a model. If you decide to use this optimization, you must enable it.
In many situations, you can selectively insert pipelines in your model and generate efficient HDL code without enabling the adaptive pipelining optimization. For example, you can selectively add pipelines next to a multiplier.
For certain design patterns, you must enable the adaptive pipelining optimization before generating code. For example, you might not be able to selectively add pipelines to the internal logic of a Discrete-Time Integrator block.
Guidelines on whether to enable adaptive pipelining:
For releases previous to R2021a, the adaptive pipelining report for your model showed that the code generator inserted adaptive pipelines. Enable adaptive pipelining when you generate code for that model.
If your model uses the blocks that are supported by the adaptive pipelining optimization and you do not selectively insert pipeline registers for these blocks, enable adaptive pipelining.
If your model uses the blocks that are supported by the adaptive pipelining optimization and you enable any of the following optimizations, also enable adaptive pipelining:
The examples Audio System That Uses Low Pass, Band Pass, and High Pass Filters and Discrete FIR Filter That Uses Resource Sharing illustrate some situations in which you must enable adaptive pipelining before generating code.
The model in this example has adaptive pipelining enabled. If you disable adaptive pipelining, the generated HDL code does not meet the timing constraints.
Open and explore this model for a Discrete FIR filter.
For the DUT Subsystem block, the HDL block property SharingFactor is set to
8. So, this subsystem uses the resource sharing optimization.
Generate Code With Adaptive Pipelining Disabled
In the Configuration Parameters dialog box, on the HDL Code Generation > Optimization > Pipelining tab, clear Adaptive pipelining.
In the HDL Workflow Advisor, set Target Frequency (MHz) to
200 and Synthesis tool to
Xilinx Vivado. Generate HDL code and perform FPGA synthesis. For more information on the code generation and synthesis steps, see HDL Code Generation and FPGA Synthesis from Simulink Model.
In the generated model, no adaptive pipelines are inserted.
The synthesis result shows a negative slack, indicating that timing constraints are not met.
Generate Code With Adaptive Pipelining Enabled
In the Configuration Parameters dialog box, on the HDL Code Generation > Optimization > Pipelining tab, select Adaptive pipelining. Generate HDL code and perform FPGA synthesis as before.
In the generated model, you can see that the code generator has inserted adaptive pipelines for the multiplier blocks.
The synthesis result shows a positive slack, indicating that timing constraints are satisfied.