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Identify design errors, prove requirements compliance, and generate tests

Simulink® Design Verifier™ uses formal methods to identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.

Simulink Design Verifier generates test cases for model coverage and custom objectives to extend existing requirements-based test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives. In addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.

Support for industry standards is available through IEC Certification Kit (for IEC 61508 and ISO 26262) and DO Qualification Kit (for DO-178).


Featured Examples


What Is Simulink Design Verifier?
Introduction to Simulink Design Verifier.

Requirements and Advanced Model Checks Workflow
Manage requirements in Simulink, perform advanced model checks, and check your model for run-time errors.

Requirements-Based Testing Workflow
Explains how to create a test using a test sequence, define a formal assessment, link test cases to requirements, run test suites, and analyze missing model test coverage.