Specify and Verify Design Requirements

Verify design against requirements, refine counterexamples by using input assumptions

Safety requirements define undesired behaviors in a model. Simulink^® Design Verifier™ uses property proving to verify that properties associated with model requirements hold under all possible input values or provides counterexamples that lead to violations. You use Simulink Design Verifier to model design requirements as properties and then Prove Properties in a Model.

Blocks

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Verify Design Requirements

Proof Assumption	Constrain signal values when proving model properties
Proof Objective	Define objectives that signals must satisfy when proving model properties
Assertion	Check whether signal is zero
Detector	Detect true duration on input and construct output true duration based on output type
Extender	Extend true duration of input
Implies	Specify condition that produces a certain response
Within Implies	Verify response occurs within desired duration
Verification Subsystem	Specify proof or test objectives without impacting simulation results or generated code

Functions

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Verify Design Requirements

`sldv.assume`	Proof assumption function for Stateflow charts and MATLAB Function blocks
`sldv.prove`	Proof objective function for Stateflow charts and MATLAB Function blocks
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvoptions`	Create design verification options object
`sldvrun`	Analyze model
`sldvreport`	Generate Simulink Design Verifier report

Topics

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Workflow for Proving Model Properties
Outlines a process for proving properties of your model.
What Is Property Proving?
Brief overview of proving properties.
Prove Properties in a Model
Provides an example that walks you through the process of proving model properties.
Use Parameter Table
An example of how to specify parameters as variables for analysis.
Specify Signal Ranges
Specify the minimum and maximum value that a signal can attain during simulation. Fully specify your design and optimize data types and the generated code by specifying the minimum and maximum value that a signal can attain during simulation.
Minimum and Maximum Input Constraints
An overview of how the Simulink Design Verifier analysis considers specified input minimum and maximum values.
Specify Input Ranges on Simulink and Stateflow Elements
Describes how the analysis handles minimum and maximum values on Simulink and Stateflow^® elements.

Requirements Modeling for Verification and Validation

What Is a Specification Model?
Overview of specification model and its use in requirements-based verification.
Model Requirements
The Simulink Design Verifier block library includes a sublibrary Example Properties.
Isolate Verification Logic with Observers
Describes the observer support for Simulink Design Verifier.
Using Specified Input Minimum and Maximum Values as Constraints
This example shows how to use input port minimum and maximum values as analysis constraints by Simulink® Design Verifier™ during both test generation and property proving.
Use Specification Models for Requirements-Based Testing
Follow a systematic approach to verify your design model against requirements.

Verification by Property Proving

Prove Properties in a Model
Provides an example that walks you through the process of proving model properties.
Design and Verify Properties in a Model
You can use Simulink® Design Verifier™ to model design requirements as properties and then prove properties in a model.
Debug Property Proving Violations by Using Model Slicer
Use Model Slicer to debug your design with assertion blocks.
Prove System-Level Properties Using Verification Model
An example that uses a verification model to prove system-level properties.
Prove Properties in a Subsystem
Explains how to prove properties in a subsystem.
Check for Specified Minimum and Maximum Value Violations
Describes how to analyze the model to verify that specified design minimum and maximum values are honored.
Specification of Input Ranges in sldvData Fields
Describes the sldvData fields for minimum and maximum input values.
Property Proving Using MATLAB Function Block
This example shows how to verify the seat belt reminder design model.
Property Proving Using MATLAB Truth Table Block
This example shows how to verify the seat belt reminder design model referenced in the top block above.
Property Proving with an Assumption Block
This example shows how to perform a Simulink® Design Verifier™ property proof using a Proof Assumption block.
Property Proving with an Invalid Property
This example shows how to find an invalid property using Simulink® Design Verifier™ property proving analysis.
Prove Properties in Large Models
Describes workflows and best practices for proving properties in large models.

Featured Examples

Validate Requirements by Analyzing Model Properties

Analyze a control system model for adherence to requirements modeled as properties, and investigate property violations by using dependency analysis.

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Property Proving Workflow for Cruise Control

Find a property violation by using Simulink® Design Verifier™ property proving analysis. You model safety requirements as properties and then verify the design model against requirements.

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Property Proving Workflow for Thrust Reverser

Verify safety properties in a thrust reverser design model. The Properties block below it contains four safety properties. Simulink® Design Verifier™ analyzes the design model and safety properties to prove correctness or to identify counterexamples. The use of model referencing eliminates the need to add verification content to the design model, allowing the verification content to exist independently from the design.

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Property Proving with Multiple Properties

Perform a property proving analysis with multiple properties. The model is configured for the analysis to attempt to prove that:

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Property Proving Workflow for Fixed-Point Cruise Control with Block Replacements

Prove properties in a fixed-point cruise control algorithm. It references the design model using model reference so that the original design model is unchanged. A block replacement rule specifies the property that checks if an overflow is possible. The verification subsystem specifies an assumption on the range of the speed input during property proving. This model configures Simulink Design Verifier to apply a block replacement to the Sum block that feeds the outport of the fixed-point PI Controller in the referenced model and return a counterexample that demonstrates an overflow.

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Use Observer Reference Blocks for Property Proving Analysis

Perform property proving analysis using Observer Reference blocks.

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Prove Properties with Requirements Table Blocks

Use a Requirements Table block and Simulink Design Verifier to prove properties of a model.

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