How to use hardware mapping with the RFDC Bus creator block for the SOC builder?

I have recently been trying to use the RFDC bus creator block with the Xilinx ZCU111 RFSoC to update the NCO from the FPGA, and I am having trouble implementing this. The problem that I am having is that there are no FPGA pins specified when using trying to build using the SOC Builder. I have assigned the model to 'External port' as is done in the example below however this still has the same issue:

Example:

Frequency Hopping Using Xilinx RFSoC Device - MATLAB & Simulink - MathWorks United Kingdom

I am wondering if anyone has used this block before and had the same issue, or has any ideas on how to map this to the correct FPGA pins?

Convert control signals into RF Data Converter real-time interface-compatible bus - Simulink - MathWorks United Kingdom

Answer 1

[SANKALP DEV]

Hello Jim,

I understand you are having trouble with the RFDC bus creator block in the SoC Builder when trying to update the’ NCO’ on the ‘ZCU111 RFSoC’. When you set your model to 'External port', it's important to ensure that the FPGA pins are correctly specified in the Xilinx Design Constraints (XDC) file.

As you have noticed in the example, the model is set up with external ports for interfacing with the FPGA pins. However, the SoC Builder tool does not automatically assign FPGA pins to your external ports; you must do this manually by editing the XDC file for your project.

For pin assignments in Xilinx tools, you typically need to specify the connections in a constraints file (XDC file).

Please refer to the attached screenshot from the Master XDC file:

In this screenshot, you can see the pin assignments for various RFDC-related signals. To map these to the correct FPGA pins in your design, you will need to:

• Open your project's XDC file in a text editor.
• Uncomment (remove the # character) the lines corresponding to the pins you want to use.
• Modify the right-hand side of the constraints to match the signal names in your Vivado project or Simulink model.
• Save the changes to your XDC file.
• Re-run the synthesis and implementation in Vivado to ensure that the pins are correctly assigned.

By following these steps, you should be able to map your design's signals to the correct FPGA pins as defined in the Master XDC file.

Hope this helps.

Thanks, and regards,

Sankalp dev