Actually this would also be my question :-) Additionally I would like to know, how to use JTAG to download the bitstream to Zedboard. Hopefully after two years, there will be an answer.
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How to reprogram the FPGA using the previously generated bitstream
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I am using HDL Workflow Advisor to program the FPGA on the ZedBoard.
The problem is, when I close the Workflow Advisor window, I have to re-synthesize the design, even if I do not change it. Is there a way to reprogram the FPGA using the previously generated bitstream without going through the Workflow Advisor again?
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