How do I parameterize signal bit width in generated DPI components?

I am trying to generate SystemVerilog DPI components from a Simulink model using HDL Coder. How can I parametrize the bit width of the model's fixed-point signals on the DPI level?

Answer 1

[MathWorks Support Team]

Parametrizing the fixed signal bit width in the generated code isn't possible since data types are fixed at compilation and code generation.

It is, however, possible to parametrize this in the model (for simulation) by controlling fixed-signals' word length using a Simulink parameter. To do this, open a block’s parameters, navigate to the ‘Signal Attributes’ tab, expand the 'Output data type' options, and set ‘Word length’ to a 'Simulink.Parameter' object that you define, as shown in the screenshot below:

The parameter's storage class should be set to ‘Model default’ or ‘ExportedGlobal’. After creating the parameter in the base workspace, you must also copy and paste it into the model workspace using the Model Explorer and make the parameter a model argument by checking the box next to ‘Argument’ in the parameter's properties.