Under Reference design parameters, there is ethernet interface instead of JTAG connection .

https://in.mathworks.com/help/hdlcoder/ug/ip-core-generation-workflow-without-an-embedded-arm-processor-xilinx-kintex-7-kc705.html

i want to generate HDL IP and implement it on kintex kc705 board ,am not to find jtag connection in hdl work flow advisor ,instead there is ethernet inteface ,while selcting ports why am not able to see external port as an option ,even if we choose axi lite/axi lite how should we code or integrate IP on fpga using microblaze ip in vivado to implement the generated hdl ip for kintex kc705 board.