Accessing GPIO and other peripherals in Soc Blockset for Xilinx ZCU216

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Patrick
Patrick el 26 de En. de 2024
Comentada: Patrick el 19 de Feb. de 2024
Hi everyone,
my research group bought a ZCU216 evaluation kit and intends to program it via Soc Blockset and the related support packages. We were able to implement the DAC and ADC outputs by using the RF data conveter block. However, we also wanted to use the other peripherals (GPIO, USB, RJ45 ethernet connector etc. ) but could not find any model block to do so.
Does someone from the community have any idea how it works?

Respuestas (1)

Raghava S N
Raghava S N el 19 de Feb. de 2024
Hi Patrick,
Please refer to the following links that detail techniques to leverage the peripherals present on the FPGA using Simulink blocks, and/or other MATLAB functionalities:
This is a SIMULINK block shipped with the SoC Blockset Support Package for Xilinx Devices.
This documentation page details the creation of a USB-ethernet interface using AXI to access memory locations.
In this community solution on MATLAB Answers, a HTTP web server IP core that transfers data between MATLAB and FPGA using the HTTP protocol is used.
You can find the exhaustive list of peripherals supported by the SoC Blockset Support Package for Xilinx Devices here - https://in.mathworks.com/help/soc/referencelist.html?type=block&s_tid=CRUX_topnav#:~:text=(Since%20R2019a)-,Peripherals,-Programmable%20Logic%20IO
  1 comentario
Patrick
Patrick el 19 de Feb. de 2024
Thank You so much for help.
I also considered to use this blocks before but it was a little bit confusing how to use them. For instance, the Digital IO block still has an output port although it was configured as output to simply set an GPIO pin to low or hight level. The purpose of this remaining output port is not addressed in the help topics. I guess this is intended for loopback or validation via scope block. Now I have implemented some GPIO outputs anyway to test it. However, the main question is how to assign a dedicated hardware pin to this software representation / block. The hardware mapping tool does not recognize it as an output port.

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