It seems that the model you’re working with cannot be deployed on the FPGA because it includes components and blocks that are not HDL code-generable. Unfortunately, this means you won’t be able to use HDL Coder for this specific model.
To ensure that your subsystems are compatible with HDL code generation, you should check whether all components and blocks within them are HDL code-generable. You can do this by looking at the extended capabilities section of each block.
For example, you can refer to the documentation for the Band-Limited Op-Amp Extended Capabilities. Only when all blocks are HDL-compatible will the option to generate code appear here:
A more effective approach is to first identify which blocks are HDL code-generable. You can do this by executing the hdllib command in the MATLAB command window. For a comprehensive list of HDL-compatible blocks, refer to the following documentation: https://www.mathworks.com/help/hdlcoder/ug/summary-of-block-implementations.html
