FIR Decimation timestack sample

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wen
wen el 5 de Feb. de 2025
anyone know if the FIR Decimation block thats compatible with HDL coder can run timestacked samples? meaning something like this. so when all channel combine it can generate waveform thats higher than FPGA clock
t0 t1
x(0) x(3)
x(1) x(4) goes to filter in parallel ----> filter
x(2) x(5)

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