Why is my Virtual bus coded as a structure?

Hello,

I am using Simulink (Matlab R2012a), with embedded coder and Stateflow. I am defining bus signals in the workspace, and then importing them into my Simulink model via inports. Those display virtual buses line styles, and when I generate my code (in C), they get implemented as structures, which should only happen if they were non-virtual, or inputed to a S-function or to a reference model. So I don't understand why it is doing so, and I can't afford those structures at this point.

I have tried to replace the inport with a "from workspace" block, but then it displays the bus as non virtual and implements it as a structure as well.

I have also tried to remove the inports, and replace all the elements with simple "from workspace" that each inport one signal. But that solution is terribly inconvenient, I need to be able to use buses, import them and not have them set as structures once builded in C.

Is there any way to achieve this?

Thank you in advance!

[Walter Roberson]

What data type were you expecting in C for a collection of information that might be different sizes and data types?

Answer 1

[Jeevan Thomas]

A bus used in Simulink is by default a "virtual bus". But if you explicitly make it non-virtual and attach a corresponding bus object in the base workspace, then Matlab generates all the signals in the bus as a structure in generated code. I believe this is exactly you've done with the inports in your model.

In addition to above, matlab generates all inputs to the model as a structure by default if the user doesn't attach corresponding signal objects for inputs. I guess this is what happened when you tried generating code with a virual bus with constituent input signals with no explicit storage class definition in base workspace for your input signals.

If you plainly make your bus as a virtual bus and define all its constituent input signals to have corresponding Simulink.Signal objects with storage class set to 'ImportedExtern' (or) 'ExportedGlobal', then you'll be able to translate signals in the virtual bus in your model as individual variables in the generated code. Please make sure to enable the checkbox options to resolve all your signals to workspace objects (as shown in fig below).

Hope it helps.

Answer 2

[Artyom]

Hello,

I'm using R2018B and have the same problem. My buses are originating from Stateflow and non-virtual by default. They create structures in generated code. But even if I convert them to virtual with Bus Selector Block or Signal Conversion Block, they are still generated as structures. If I define the simulink signal at the output of such block and attach other than auto storage class to it, Simulink generates error:

The Simulink.Signal object specified on the line originating from output port 1 of 'Controller/Signal Conversion' is not allowed because it cannot be mapped uniquely to a non-virtual signal. To resolve this issue, consider changing the "Output" option of the Signal Conversion block to "Nonvirtual bus".

I want the members of the output bus to be defined like unique variables with the names as in the bus in generated C code and ImportedExtern Storage class and not as struct. How to achieve that without manual bus selector and individual signal naming?