How can I use vhdl generics when I generate a matlab system object from my vhdl code with HDL verifier?
Mostrar comentarios más antiguos
I want to generate a matlab system object from my vhdl code with HDL verifier, for using it as FPGA in the loop. Following matlab documentation's steps is quite easy to do it. The problem is that my code contains vhdl generics. So, once matlab generates the system object, I would like to be able to change the value of the generics, but I don´t know how to do it.
Respuesta aceptada
Más respuestas (1)
Tim McBrayer
el 19 de Sept. de 2016
0 votos
It sounds like you are trying to model existing handwritten VHDL that uses generics in its interface, in Simulink, and using a System Object. And, the HDL Coder implementation of System Objects don't support generics.
One thing you could try is to wrap the System Object block inside a subsystem. This may help in one of two ways depending on your circumstances. If you are trying to black-box your existing VHDL code into a larger Simulink design, you can set the HDL Architecture of the Subsystem to a black box and connect the generics up through that interface. Alternatively, you can investigate using a masked subsystem and setting 'mask parameters as generics' in HDL Coder.
1 comentario
Eduardo Lasarte
el 19 de Sept. de 2016
Categorías
Más información sobre HDL Coder en Centro de ayuda y File Exchange.
Productos
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!