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How to do speed optimizations with/in feedback Loops? -Simulink HDL Coder

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Lars Boschert
Lars Boschert on 9 Nov 2017
Answered: Kiran Kintali on 20 Oct 2020
Hello Community, I am using Simulink HDL Coder with Matlab r2017a. However, I have an implementation of a PI Controller and try to optimize the clockspeed for my FPGA design. But some of the blocks(e.g Multiplier for Kp and KI, atleast it tells me so) to optimize are arranged in a feedback Loop and HDL Coder refuses to insert (adaptive) Pipeline Registers and also delay balancing is not possible for delays in Feedback Loops.
Do you have a nice and accurate workaround for doing speed optimization in feedback-Loops (in General)?
Thank you, Lars

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Lars Boschert
Lars Boschert on 13 Nov 2017
The answer given in the question on top is also working for Speed optimizations(adaptive Pipelining): "consider moving the feedback loop into the subsystem where sharing is occuring".
I did that but my mistake was that the discrete Integrator, which is build with a "sum" and an "UnitDelay", also results in a Feedback path/Loop.

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Answers (1)

Kiran Kintali
Kiran Kintali on 20 Oct 2020
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features.
Clock Rate Pipelining
This example shows how to apply clock rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate pipelining, see Clock-Rate Pipelining.
HDL Coder Clock Rate Pipelining, Part 1: Introduction
HDL Coder Clock Rate Pipelining, Part 2: Optimization


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