Where can I set output and input port of an HDL-supported Simulink model?

I am using a Simulink model commqpsktxhdl. I have managed to output HDL code and I found that there 3 inputs including clk, clk-enable and reset and 3 output ports including ce_out, QPSK_RRC_Shaped_re, and QPSK_RRC_Shaped_im. However, I do not find where can I set all these ports. And what I want to do is to change its input data so I need to add input data port. Any suggestions?

Answer 1

[Kiran Kintali]

Are you looking for how to simulate the generated code? If yes, please try to generate HDL test bench and look at how these clock, clock enable and reset pins are driven.

If you looking interfacing the HDLCoder generated logic to handwritten code look into product demos. Please also check out our automated IP core or turnkey workflows for target specific workflows.

[luckfy zhang]

Thanks for your reply. I mean the later part of your answer. In other words, I am wondering where can I set input and output ports of a Simulink model, which could be transformed to HDL model ports. Where can I find "turnkey workflow" and reference of automated IP? I do have checked reference provided by Mathworks on commqpsktxhdl, but I didn't find that kind of settings.

https://ww2.mathworks.cn/help/comm/examples/hdl-optimized-qpsk-transmitter.html