when using Design Error Detection and generate test, Simulink Design Verifier has exceeded the maximum processing time

when using Design Error Detection and generate test, Simulink Design Verifier has exceeded the maximum processing time,even if using the exsample

Answer 1

[Rishabh Rathore]

One of the reasons for this could be that the 'maximum analysis time' in configuration parameter box is very small.

You can increase the 'maximum processing time' yourself.

In 'Configuration Parameters', select 'Design Verifier' from left panel and then in the 'Maximum analysis time' field, specify an appropriate time in seconds.

[huan xu]

 the 'maximum analysis time' have been set 3600 seconds,but it also can not work, such as there is 133 objects, the 115 can process in 3 minites, when it process the 116th objects, it will last to the 'maximum analysis time' and can not found the error message why the 116th objects can not be analysis. how to check that?

[Rishabh Rathore]

Is this when using example model or your own model. If example, can you tell me which example are you using.

[huan xu]

Now I using the example mode 'sldvdemo_fuelsys_logic' in 2016b to generate test mode ,it can not process after the 119th object, and no matter what the example mode or our own mode, I hope I can found the reason why it can not be process OK, how to check and modify.

[huan xu]

Is there any method to check and process this problem?