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Is there something like code replacement when using HDL Coder?

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Felix Schneider
Felix Schneider on 30 Jul 2018
Answered: Kiran Kintali on 20 Oct 2020
I'm working on a HDL project that requires combining external HDL-modules (specifically FIFOs from the Xilinx-generator) with the Simulink-generated HDL Code (see my related question [1]).
I'm attaching the picture of the general principle. While in simulation, the synchronization subsystems contain just Rate Transition blocks but in the synthesized HDL Code they should be replaced by an external verilog or VHDL-module, that was generated from the Xilinx FIFO-generator.
Is there a way to exclude subsystems from HDL-Code generation and instead replace them with external modules?
Thanks in advance,


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Answers (1)

Kiran Kintali
Kiran Kintali on 20 Oct 2020
The simplest approach for incorporating external IP into your HDL Coder Design is to create a black box interface for a subsystem that models the behavior of the external IP. Please see this documentation page for details on generating a black box interface:
The steps to generate a black box interface are as follows:
1) Create a subsystem that models the external IP's behavior
2) Right-click on the block and select HDL Code > HDL Block Properties
3) Change the "Architecture" to 'BlackBox'
The generated HDL component from this subsystem only includes the HDL input and output port definitions for the subsystem. You can then integrate your external IP into the generated code by either of the following options:
b) In HDL Block Properties for the black box subsysytem, specify the 'EntityName' to match the name of the HDL file. Then, in the top-level DUT block, specify the path to this file under HDL Code > HDL Block Properties > Target Specification > IPCoreAdditionalFiles.


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