I'm working on a HDL project that requires combining external HDL-modules (specifically FIFOs from the Xilinx-generator) with the Simulink-generated HDL Code (see my related question ).
I'm attaching the picture of the general principle. While in simulation, the synchronization subsystems contain just Rate Transition blocks but in the synthesized HDL Code they should be replaced by an external verilog or VHDL-module, that was generated from the Xilinx FIFO-generator.
Is there a way to exclude subsystems from HDL-Code generation and instead replace them with external modules?
Thanks in advance,