HDL Coder and HDL Verifier

Hello,

Sorry for asking so many questions about the HDL Coder and Verifier recently it is just that I have never started a project like this before, and I am trying to create a list of everything I need.

Background: I am testing FPGA portability between two different FPGAs; the Spartan 6 and Arria II Gx.

I have a list of questions.

1) What is the difference between the Xilinx Spartan 6 DSP Development Kit from Simulink and the Xilinx Spartan 6 DSP Development Kit from Avnet? Both provide the same FPGA, so do I still need the one from Avnet?

2) The product that used the FPGA used Synopsis as its synthesis tool. Do I need Synopsis to use the HDL Coder?

3) The HDL Verifier needs a simulator, but it also has FPGA hardware-in-the-loop. With that being said, can I use Simulink as the simulator?

4) Can I used the same FPGA 'board' to interface the FPGA to the computer?

Some of these questions I have asked already, but I just need to clarify some things and put all my questions together.

Thanks, Natalie

Answer 1

[Tim McBrayer]

I cannot answer question 1: I'm not familiar with the development boards.

For question 2: HDL Coder's Workflow Advisor is integrated with Xilinx ISE and Altera Quartus. You can generate code with HDL Coder, but you cannot automatically set up projects and run other synthesis tools, either from Synopsys or from another vendor.

For question 3: HDL Verifier has two separate modes: one co-simulates with a HDL simulator, and the other uses FPGA-in-loop simulation. Both of these require Simulink as the master simulator. They differ in the fashion that your generated HDL is exercised. With cosimulation, your HDL is simulated by a 3rd-party HDL simulator. With FIL, your synthesized HDL code is loaded onto a FPGA located on one of a set of supported FPGA development boards, and the programmed FPGA participates in your Simulink simulation.

For question 4: yes, this is the supported method. Your FPGA development board is typically connected by USB or Ethernet to your host PC. This connection is used both for programming the FPGA on the board and for FIL simulation.

Answer 2

[Natalie Cranston]

Thank you!

Going back to Question 3: Is it possible to do run Synopsys using an EDA script?

Going back to Question 4: I didn't quite word my question correctly. From my understanding, there is a development board used for programming the FPGA and a board used to interface to the PC. Is it possible to use the same board for interfacing two different types of FPGAs?

Thanks again, Natalie

[Tim McBrayer]

If you are familiar with the scripting language for a tool, you can have HDL Coder generate custom scripts for you, based off the files that are created in a given run. This is not integrated with the Workflow Advisor.

I believe that the boards are typically specific to a given FPGA, as detailed in the documentation at http://www.mathworks.com/help/toolbox/edalink/gs/bsm6iqf-8.html#bta7b6u-1 .