I have a Simulink design that I want to build into a custom IP block to deploy on a Zynq FPGA target using HDL Coder. The concept is that the block takes some data from Block RAM, performs some compuations on that data and saves the results in Block RAM. The design consists mainly of fixed-point embedded Matlab blocks in a Simulink subsystem. There is also a Stateflow controller that manages how the computation block takes data from Block RAM and how the results are stored back in Block RAM. The design is simulated in Simulink and functionally appears to do what is needed.
The problem is working out how the Stateflow controller knows at what point the data produced by the computation block is valid. Typically from being presented with the first item of data from Block RAM it might be many clock cycles before a valid result is produced. The Stateflow controller must store the results in Block RAM only when they are valid. The timing properties cannot be characterised by HDL Coder as there is no data available for the embedded Matlab blocks.
Is there a way to work out the latency through the model without having the characterisation data?
Alternatively is there some construct that can be built into the model that would for example produce a trigger when the first valid result becomes available?
This is very akin to using the 'FFT HDL Optimized' block in the DSP System Toolbox HDL Support library. This block displays the latency in its mask according to the particular configuration as well as providing output signals to show when valid data is available. This is exactly what I want to do in my custom IP block but I cannot see how to go about this.