Problem in implementing Band-pass filter using FIR and FPGADataCaptureIP

I have implemented bandpass filter (14-17MHz) on FPGA (zedboard) using FIR IP core, simulation works fine. But after implementation on hardware, the results shows that one frequency peak is detected on 15MHz but two other peaks are detected on 5MHz and 35 MHz frequency also. The baseband signal is 10MHz and carrier is 25MHz. The output of mixer is passed through bandpass filter which have to attanuate the (fc+fm = 35MHz) and allow only (fc-fm = 15MHz), but practically it allows both the frequencies. Can anyone help regarding this?

Thanks.