HDL Coder Filter Latency

Hi

Ive complied a fully paralell FIR filter using the FilterDesigner and HDL Coder and it reported the latency as 2. I am struggling to understand what the latency is exactly, is it the number of clocks required for a valid output? - 1 clock for multiplication and another for summing, but if so would the delay pipeline not also require a clock cycle?

-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 65
-- Stable            : Yes
-- Linear Phase      : Yes (Type 1)
-- Arithmetic        : fixed
-- Numerator         : s16,15 -> [-1 1)
-- Input             : s16,15 -> [-1 1)
-- Filter Internals  : Full Precision
--   Output          : s33,30 -> [-4 4)  (auto determined)
--   Product         : s31,30 -> [-1 1)  (auto determined)
--   Accumulator     : s33,30 -> [-4 4)  (auto determined)
--   Round Mode      : No rounding
--   Overflow Mode   : No overflow
-- -------------------------------------------------------------

Thanks in advance.

Answer 1

[Aman Vyas]

Hi,

Latency is defined as the total number of clock cycles required in obtaining the output.

It will depend which path are you seeing for delay pipeline. If the path you are seeing for output that will require 2 cycles.

For more information read the following article:

https://in.mathworks.com/help/dsp/ug/delay-and-latency.html

Hope this helps !

[Ewan Mackenzie]

Exactly what I was looking for, thank you