Does Simulink Design Verifier dead logic analysis depend on model inputs?

Why do I see different dead logic results when using a harness to pass inputs (with "Constant" blocks) as opposed to using "Inport" blocks?

Answer 1

[MathWorks Support Team]

By default, Simulink Design Verifier will consider the full range of possible input values for only the root-level inports in the model. The possible values for all other model elements are treated as a function of the inports (and global variables). In the case of passing inputs with the "Constant" block, more dead logic will be detected since it will only consider those particular inputs and not the full range.