In the example, when you send data to SPI transmit block, the data continuously shifts of the transmit register. This in turn causes the data to be read back into the receive register which will be stored in receive FIFO. So you will keep on getting data in receive register as long as you send data using Transmit block.
Here we have configured the interrupt to be triggered when FIFO gets 4 or more receive values. Inside the interrupt subsystem, we have configured to read 4 words from receive block. Once the data is read the next receive interrupt is triggered only when the data received in FIFO becomes 4. This configuration is done by Browse to Hardware Implementation > Target Hardware Resources > SPI_A, select Enable Rx interrupt, and set FIFO interrupt level(Rx) to 4.
Also ensure SIMO, SOMI, CLK, and STE pin assignment are configured correctly so that the SPI reading of data is correct. Pick a proper STE pin value even though you are using internal loopback in order to get proper data while reading in SPI receive block.