Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

1 visualización (últimos 30 días)
Eduardo Flores
Eduardo Flores el 27 de Dic. de 2020
Respondida: YP el 21 de Nov. de 2022
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
  1 comentario
Cau Tran
Cau Tran el 11 de Ag. de 2022
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.

Iniciar sesión para comentar.

Iniciar sesión para responder a esta pregunta.

Respuestas (1)

YP
YP el 21 de Nov. de 2022
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

Categorías

Más información sobre FPGA-in-the-Loop en Help Center y File Exchange.

Etiquetas

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by