Best Practices for Simulink HDL Coder Development
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Hi,
I am new to HDL Coder/Verifier. I was wondering if someone has documented best practices for developing HDL Coder designs.
I am hoping that these best practices help in the following way:
- generate very readable code;
- make signal timing alignment evident in the Simulink model;
- create clean hierarchies;
- address naming conventions;
- discuss how to use libraries effectively;
- discuss how to use subsystems effectively;
- how to specify the top level interface;
- ...
I've used System Generator in the past, but due to the greater abstraction with HDL Coder, I'm less clear on how to best use this tool.
Thanks, Phil
2 comentarios
Kiran Kintali
el 17 de Abr. de 2013
Hi Philippe,
HDLCoder generates readable and traceable HDL code from a Simulink model or MATLAB code that is both user and synthesis tool friendly. Let us know what constructs in HDLCoder do not meet this requirement. If you use the blocks in HDL supported subset of Simulink library (type 'hdllib' to see this list) you should get synthesizable HDL code. Please use 'checkhdl' command to get a quick overview of unsupported options on the blocks before code generation.
HDLCoder maps Simulink sample times and Simulink rates to clocks, clock enables and resets (what we call internally as a clock bundle). There are variety of timing schemes supported by HDL Coder (map your multiple rates in the model to a single clock and clock enables generated by a timing controller or map them to multiple clocks routed to the top level DUT). Restrictions apply.
HDLCoder treats Simulink hierarchy (susbsytems) as module/entity hierarchy. Using reusable atomic subsystems you can reduce the number of generated files. Also there is FlattenHierarchy option on subsystems to control the level of hierarchy generated in the HDL files.
HDLCoder generates very readable code and all the identifiers in Simulink (block, subsystem, signal, port names) are preserved in the generated code. You can control these and other internally generated control signal (in addition their prefixes and suffixes) in various ways using code generation options. HDLCoder also optionally generates a coding standard report that shows potential naming standard and naming convention violations in your generated code and how to fix them.
HDLCoder provides options to generate compilation, synthesis, simulation and lint scripts, where you could add additional libraries and custom code.
Hope I have answered some of the questions, please refer to documentation for more details.
Respuestas (1)
Kiran Kintali
el 24 de Mayo de 2021
HDL Coder Evaluation Reference Guide
Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:
* Setting up your MATLAB algorithm or Simulink model for HDL code generation
* How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
* Tips and advanced techniques for HDL code generation
* Code generation settings for specific FPGA/SoC targets, including AXI interfaces
* Converting to fixed-point or utilizing native floating point
* Optimizing for various goals and targets
* Verifying your generated code
It also includes examples to illustrate selected concepts.
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