Input Sample rate of HDL LTE Cell Search module

Hi,

I'm working with LTE HDL Cell Search example to generate VHDL code. (LTE HDL Cell Search)

When simulating the VHDL code generated by Matlab on Vivado, I see that every sample at the input takes 2 cycles of clock like the image below.

The document said that the input sample rate is 30.72 Msps, I understand that 30.72 Msps is the sample rate of ADC and different with clock rate, it makes me a little bit confused about why the sample takes 2 cycles clock here because in the actual case, it takes only 1 cycle clock?

Could you help me with my problem?

Thank you so much!

Answer 1

[Garrey Rice]

The HDL code generated by the LTE HDL Cell Search model requires a clock rate of at least twice the input sampling rate. Therefore if the input sampling rate is 30.72 MHz (as modeled in Simulink) then a clock rate of at least 61.44 MHz is required. There are Upsample blocks in the ltehdlCellSearch/Cell Search HDL/Downlink Sync Demod (ltehdlDownlinkSyncDemod) subsystem which raise the sampling rate from 30.72MHz to 61.44MHz. HDL Coder recognises that this is the highest rate in the design and designates it as the clock rate. This is reflected in the HDL testbench and explains why the data being passed into the design only changes every two clock cycles.

[Tuan Hoang Dinh]

Hi Garrey Rice,

Thanks for spending time with my problem.

From your answer, I have understood the way block works.

Best regards,

Tuan