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I want to convert matlab code to verilog for my image processing project using hdl coder, i have the code but i dont know how to divide my code into function and test bench, please help me. I m using matlab r2018a version.
<https://www.mathworks.com/examples/vision-hdl/mw/visionhdl-ex64676005-accelerate-a-pixel-streaming-design-using-matlab-coder He...

más de 7 años hace | 1

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Is it possible for Filter Design HDL coder to generate a FIR filter whose sampling rate is higher than clock rate?
This is available with HDL Coder and the FIR block in DSP System Toolbox. Please take a look at this <https://www.mathworks.com...

más de 7 años hace | 1

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HDL Sinusiod with phase offset and variable frequency
You may be able to use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html HDL Optimized NCO> to meet your needs.

más de 7 años hace | 0

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Simulink: How to implement an SRRC filter in HDL coder?
You can use <https://www.mathworks.com/products/filterhdl/features.html Filter Design HDL Coder> to implement a Farrow or an FIR...

más de 7 años hace | 0

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Dual Port Ram - Output Port Widths or Dimension Error
Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block ha...

más de 7 años hace | 0

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How to avoid the division operator from hdlcoder?
You can try using the <https://www.mathworks.com/help/simulink/slref/hdlreciprocal.html HDL reciprocal block> followed by a mult...

más de 7 años hace | 0

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HDL NCO: How do I set the fraction length for the phase accumulator?
The accumulator and quantizer do not have fractional bits. You can scale your input phase offset to match the accumulator and qu...

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HDL Coder Filter - Latency and Clock rate
I assume that you are sharing resources in the filter implementation leading to the 201x clock requirement. If your design sy...

más de 7 años hace | 0

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Why my Integer Fir on filterbuilder gives me zero coefficients?
Could you post the coefficients (at least the min/max values)? What is your input data type? For implementation onto an FPGA, y...

más de 7 años hace | 0

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HDL Coder Filter - Latency and Clock rate
The latency of 3 samples is not the group delay of the filter. It specified the number of pipeline delays in the data processing...

más de 7 años hace | 0

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HDL workflow Advisor image
This <https://www.mathworks.com/products/vision-hdl.html Vision HDL Toolbox page> shows the capabilities provided for image proc...

más de 7 años hace | 0

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Lane Detection with Zynq-Based Hardware - Pixel-Stream Model
You also need to download the <https://www.mathworks.com/hardware-support/zynq-vision.html Xilinx Zynq Support from Computer Vis...

más de 7 años hace | 0

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Generating Verilog for Butterworth IIR lowpass filter, incorrect simulation
Can you try running the HDL code and testbench in ModelSim to see if it passes? If it does, that means that HDL code matches the...

casi 8 años hace | 0

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buffer block inside enabled subsystem
What is the purpose of using the buffer block in an enabled subsystem? You cannot really have 512 samples coming out of an FPGA ...

casi 8 años hace | 0

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this is our matlab code for image enhancement using power law at gamma=1.01,but we are getting error in function while compiling due to floating number(1.01).we are able to convert to verilog code using hdl coder at gamma=1 but not at gamma=1.01.help
You can use the Lookup table implementation for the <https://www.mathworks.com/help/visionhdl/ref/gammacorrector.html Gamma Corr...

casi 8 años hace | 0

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buffer quivalent block in HDL coder
Starting in R2018a, you can choose natural or bit-reversed order for the FFT block with vector input.

casi 8 años hace | 0

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buffer quivalent block in HDL coder
If you are using the <https://www.mathworks.com/help/dsp/ref/ffthdloptimized.html HDL Optimized FFT block> , I suggest you use a...

casi 8 años hace | 0

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Delaying FFT by a specified delay factor in simulink
I suggest using the dual port RAM. You can write the output of the FFT into the RAM as available. The read port will be controll...

casi 8 años hace | 0

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Issue : Can't find SimpleDualPortRAM_generic-verilog.pvl
Could you print out a list of source files generated by HDL Coder and upload the model? It seems that the Dual Port RAM code was...

casi 8 años hace | 0

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how to give vector as input to complex to magnitude angle hdl block
You can pass in the 64x1 samples to the <https://www.mathworks.com/help/dsp/ref/unbuffer.html Unbuffer block> which will send ou...

casi 8 años hace | 0

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HDLCODER support function invoke function?
You can run this through the HDL code generation workflow. Any functions that are supported for HDL will generate HDL code. Func...

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How to use extended word length and fraction in HDLFFT?
Satish, I am not able to reproduce the error. Here is my code. close all N = 8; ddc_out = randi([0 1],8,1); y_f...

casi 8 años hace | 1

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No system or file called 'FFTHDLOptimizedExample_Burst' found.
You will need the DSP System Toolbox product for this example. Type *_ver dsp_* at the MATLAB prompt to see if you have this pro...

alrededor de 8 años hace | 0

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How to use fft in matlab hdl code to generate hdl code
Here is an <https://www.mathworks.com/help/dsp/examples/generate-hdl-code-for-fft-hdl-optimized-block.html example> of how to ge...

alrededor de 8 años hace | 0

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Triggering video stream with AND gate.
I believe that Kiran is asking you to put the enabled subsystem into a subsystem. TO do this, select the enabled subsystem and h...

alrededor de 8 años hace | 0

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How to generate Sine and triangle wave using HDL blockset?
You can use the <https://www.mathworks.com/help/dsp/ref/ncohdloptimized.html NCO HDL Optimized block> to generate a Sine wave. ...

alrededor de 8 años hace | 0

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When would HDL Coder support FFT with run time configurable transform point size ?
Could you please give some use cases for support so that we can consider the request for future releases?

alrededor de 8 años hace | 0

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Why my output image file turn out grayscale?
You have two issues with your model. # Change the Output Buffer Size setting for the Buffer block to 512*512*3. # Instead of...

más de 8 años hace | 0

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How to set input and output data types separately for a filter when using generatehdl()?
The output of cicCompCascade is the output of the filter, and this is what Filter Design HDL Coder uses as the output type. Plea...

más de 8 años hace | 0

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questions about Filter Design HDL Coder
Hi, You can post your question here or contact MathWorks support. Thanks, Bharath

más de 8 años hace | 0