How to Shift ASIC and FPGA Verification Left using MATLAB and Simulink
Learn how to improve verification of ASIC and FPGA implementation of MATLAB algorithms and Simulink models through the combination of model verification and validation techniques with generation and verification of RTL code.
Functional verification of ASICs and FPGAs accounts for 50-70 percent of total design effort, and surveys show that achieving coverage closure is the single biggest challenge that design teams face before achieving signoff.
In this webinar, we will cover these topics to address verification challenges.
- Developing test cases to verify high-level functional behavior
- Evaluating model coverage metrics and expanding model coverage
- Generating verification components directly from the verified system-level models
- Generating RTL from MATLAB code and Simulink models
- Establishing traceability from requirements through models, RTL implementations and ASIC / FPGA verification environments.
MathWorks engineers will demonstrate use of these techniques on example designs verified using the Universal Verification Methodology (UVM).
About the Presenters
Mark Lin in an advance application engineer supporting ASIC/FPGA workflows who specializes in digital design verification. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a BS degree in electrical engineering from California State University of Los Angeles.
Eric Cigan is the principal product marketing manager at MathWorks for ASIC and FPGA verification. Prior to joining MathWorks, he held technical marketing roles at MathStar, AccelChip, and Mentor Graphics. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.
Recorded: 26 Sep 2019
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