Synthesis and Timing Analysis

R2026b
Generate synthesis scripts and retrieve synthesis results

Generate scripts to compile, simulate, and synthesize generated code for electronic design automation (EDA) tools. You can also generate TCL commands for specific synthesis tools by specifying synthesis objectives such as area optimization, compile optimization, or speed optimization in the HDL Workflow Advisor.

Use HDL Workflow Advisor, to generate an RTL lint check report for generic ASIC or FPGA devices by using Synopsys® SpyGlass Lint tool. You can also perform the synthesis for the generic ASIC devices by using Cadence® Genus synthesis tool.

Functions

hdlsetuptoolpathSet up system environment to access FPGA synthesis software

Model Settings

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Generate EDA scriptsEnable generation of third-party electronic design automation script files
Compile file postfixPostfix to append to DUT or test bench name for compilation script file name
Compile initializationFormat name to use to write Init section of compilation script
Compile command for VHDLFormat name to use to write Cmd section of compilation script for VHDL
Compile command for Verilog or SystemVerilogFormat name to use to write Cmd section of compilation script for Verilog or SystemVerilog
Compile terminationFormat name to use to write termination section of compilation script
Simulation file postfixPostfix to append to DUT or test bench name
Simulation initializationFormat name to use to write initialization section of simulation script
Simulation commandFormat name to use to write simulation command
Simulation waveform viewing commandWaveform viewing command to write to simulation script
Simulation terminationFormat name to write to write termination section of simulation script
Simulator flagsSimulator flags to apply to generated compilation scripts
Choose synthesis toolSpecify synthesis tool for which to generate synthesis scripts
Synthesis file postfixPostfix to append to file name
Synthesis initializationFormat name to use to write initialization section of synthesis script
Synthesis commandFormat name to use to write synthesis command
Synthesis terminationFormat name to use to write termination section of synthesis script
Additional files to add to synthesis projectAdditional HDL or constraint files
Choose HDL lint toolSpecify HDL lint tool for which to generate lint scripts
Lint initializationFormat name to use to write initialization section of HDL lint script
Lint commandFormat name to use to write command for HDL lint script
Lint terminationFormat to use to write termination section of HDL lint script

Topics

Tool Script

Synthesis

Featured Examples

Generate RTL Lint Check Report Using HDL Workflow Advisor and Synopsys SpyGlass Lint Tool

Generate RTL Lint Check Report Using HDL Workflow Advisor and Synopsys SpyGlass Lint Tool

Generate RTL lint check report using HDL Workflow Advisor and SpyGlass Lint tool.

Generate HDL Code and Perform Synthesis Using Cadence Genus on ASIC Devices

Generate HDL Code and Perform Synthesis Using Cadence Genus on ASIC Devices

Generate HDL code and perform synthesis using HDL Workflow Advisor and Cadence Genus on ASIC devices.

Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus

Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus

Use multicycle path constraints with HDL Workflow Advisor and Cadence Genus synthesis tools to meet the timing requirements for ASIC devices.

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Perform Synthesis and Implementation Using Synplify Elite

Perform Synthesis and Implementation Using Synplify Elite

Generate HDL code and perform logic synthesis using Synplify® Elite, and place-and-route using AMD® Vivado® in HDL Workflow Advisor.

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Perform Logic Synthesis Using Design Compiler

Perform Logic Synthesis Using Design Compiler

Generate HDL code and perform logic synthesis using Synplify Design Compiler in HDL Workflow Advisor.